2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-08-27 05:27:53 +02:00
|
|
|
global.BPredUnit.BTBHits 65676436 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 73156986 # Number of BTB lookups
|
|
|
|
|
global.BPredUnit.RASInCorrect 166 # Number of incorrect RAS predictions.
|
|
|
|
|
global.BPredUnit.condIncorrect 4207318 # Number of conditional branches incorrect
|
|
|
|
|
global.BPredUnit.condPredicted 70088985 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 76017379 # Number of BP lookups
|
|
|
|
|
global.BPredUnit.usedRAS 1692882 # Number of times the RAS was used to get a target.
|
|
|
|
|
host_inst_rate 211348 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 182448 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 2675.93 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 60738573 # Simulator tick rate (ticks/s)
|
|
|
|
|
memdepunit.memDep.conflictingLoads 16721732 # Number of conflicting loads.
|
|
|
|
|
memdepunit.memDep.conflictingStores 11866335 # Number of conflicting stores.
|
|
|
|
|
memdepunit.memDep.insertedLoads 126743752 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
memdepunit.memDep.insertedStores 43041597 # Number of stores inserted to the mem dependence unit.
|
2006-10-12 21:04:14 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2006-12-05 01:07:00 +01:00
|
|
|
sim_insts 565552443 # Number of instructions simulated
|
2007-08-27 05:27:53 +02:00
|
|
|
sim_seconds 0.162532 # Number of seconds simulated
|
|
|
|
|
sim_ticks 162531946000 # Number of ticks simulated
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:branches 62547159 # Number of branches committed
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 20242536 # number cycles where commit BW limit reached
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 315316083
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-08-27 05:27:53 +02:00
|
|
|
0 101801168 3228.54%
|
|
|
|
|
1 100686280 3193.19%
|
|
|
|
|
2 36605446 1160.91%
|
|
|
|
|
3 9846862 312.29%
|
|
|
|
|
4 9756830 309.43%
|
|
|
|
|
5 22230548 705.02%
|
|
|
|
|
6 12726034 403.60%
|
|
|
|
|
7 1420379 45.05%
|
|
|
|
|
8 20242536 641.98%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:count 601856963 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 115049510 # Number of loads committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.COM:refs 154862033 # Number of memory references committed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.commit.branchMispredicts 4206693 # The number of times a branch was mispredicted
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 60367294 # The number of squashed insts skipped by commit
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.cpi 0.574772 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.574772 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 111194484 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 32074.811872 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5025.209404 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 110978275 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 6934863000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.001944 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 216209 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 901354 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 1086495500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 216209 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 37821041 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 31690.076841 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5379.514968 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 37483812 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 10686812923 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.008916 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 337229 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 1630280 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1814128453 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.008916 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 337229 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs 500 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets 1750 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_refs 314.126008 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 7000 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dcache.demand_accesses 149015525 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 31840.379452 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 5241.100093 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 148462087 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 17621675923 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.003714 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 553438 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 2531634 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 2900623953 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.003714 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 553438 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dcache.overall_accesses 149015525 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 31840.379452 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 5241.100093 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dcache.overall_hits 148462087 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 17621675923 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.003714 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 553438 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 2531634 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 2900623953 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.003714 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 553438 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dcache.replacements 468780 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 472876 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dcache.tagsinuse 4095.312024 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 148542650 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 41060000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 334093 # number of writebacks
|
|
|
|
|
system.cpu.decode.DECODE:BlockedCycles 42961711 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 4159669 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 688665550 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 143212697 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 123677184 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 9747531 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 1998 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 5464492 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.dtb.accesses 162979892 # DTB accesses
|
|
|
|
|
system.cpu.dtb.acv 0 # DTB access violations
|
|
|
|
|
system.cpu.dtb.hits 162933690 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 46202 # DTB misses
|
|
|
|
|
system.cpu.dtb.read_accesses 122208199 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.dtb.read_hits 122186821 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 21378 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_accesses 40771693 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.dtb.write_hits 40746869 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 24824 # DTB write misses
|
|
|
|
|
system.cpu.fetch.Branches 76017379 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 65923007 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 196871509 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 1349795 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 697858274 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 4233156 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.233854 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 65923007 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 67369318 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 2.146836 # Number of inst fetches per cycle
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 325063615
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-08-27 05:27:53 +02:00
|
|
|
0 194115151 5971.61%
|
|
|
|
|
1 10367448 318.94%
|
|
|
|
|
2 15852914 487.69%
|
|
|
|
|
3 14602370 449.22%
|
|
|
|
|
4 12321515 379.05%
|
|
|
|
|
5 14794025 455.11%
|
|
|
|
|
6 6009823 184.88%
|
|
|
|
|
7 3340187 102.75%
|
|
|
|
|
8 53660182 1650.76%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 65922920 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 7890.798226 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5470.620843 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 65922018 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 7117500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 87 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 4934500 # number of ReadReq MSHR miss cycles
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.avg_refs 73084.277162 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.demand_accesses 65922920 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 7890.798226 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 5470.620843 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 65922018 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 7117500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 902 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 4934500 # number of demand (read+write) MSHR miss cycles
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.overall_accesses 65922920 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 7890.798226 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 5470.620843 # average overall mshr miss latency
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.overall_hits 65922018 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 7117500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 902 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 87 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 4934500 # number of overall MSHR miss cycles
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.replacements 32 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.icache.tagsinuse 770.534444 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 65922018 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.idleCycles 190397 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 67319692 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 42991424 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.842347 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 163918711 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 41167815 # Number of stores executed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iew.WB:consumers 490977460 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 595732364 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.805927 # average fanout of values written-back
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iew.WB:producers 395691865 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.832664 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 596897738 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 4671822 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 211982 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 126743752 # Number of dispatched load instructions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 3268805 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 43041597 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 662373944 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 122750896 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 6416858 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 598879902 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1310 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 9747531 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 36871 # Number of cycles IEW is unblocking
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 10085062 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 15402 # Number of memory responses ignored because the instruction is squashed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 28955 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 5897 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 11694242 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 3229074 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 28955 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 540642 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 4131180 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 1.739821 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.739821 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 605296760 # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2007-08-27 05:27:53 +02:00
|
|
|
No_OpClass 0 0.00% # Type of FU issued
|
|
|
|
|
IntAlu 438526639 72.45% # Type of FU issued
|
|
|
|
|
IntMult 6526 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
2007-08-27 05:27:53 +02:00
|
|
|
FloatAdd 29 0.00% # Type of FU issued
|
2007-04-27 20:35:58 +02:00
|
|
|
FloatCmp 5 0.00% # Type of FU issued
|
2006-12-05 01:07:00 +01:00
|
|
|
FloatCvt 5 0.00% # Type of FU issued
|
2007-04-27 20:35:58 +02:00
|
|
|
FloatMult 4 0.00% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2007-08-27 05:27:53 +02:00
|
|
|
MemRead 124781721 20.61% # Type of FU issued
|
|
|
|
|
MemWrite 41981831 6.94% # Type of FU issued
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 6717566 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011098 # FU busy rate (busy events/executed inst)
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
2007-08-27 05:27:53 +02:00
|
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntAlu 5391256 80.26% # attempts to use FU when none available
|
|
|
|
|
IntMult 67 0.00% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2007-08-27 05:27:53 +02:00
|
|
|
MemRead 838838 12.49% # attempts to use FU when none available
|
|
|
|
|
MemWrite 487405 7.26% # attempts to use FU when none available
|
2006-10-12 21:04:14 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 325063615
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-08-27 05:27:53 +02:00
|
|
|
0 85796359 2639.37%
|
|
|
|
|
1 67542387 2077.82%
|
|
|
|
|
2 80092036 2463.89%
|
|
|
|
|
3 31532999 970.06%
|
|
|
|
|
4 32045835 985.83%
|
|
|
|
|
5 15660373 481.76%
|
|
|
|
|
6 10783606 331.74%
|
|
|
|
|
7 1095697 33.71%
|
|
|
|
|
8 514323 15.82%
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 1.862087 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 619382498 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 605296760 # Number of instructions issued
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 52509739 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 11652 # Number of squashed instructions issued
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 28327252 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.itb.accesses 65923045 # ITB accesses
|
|
|
|
|
system.cpu.itb.acv 0 # ITB acv
|
|
|
|
|
system.cpu.itb.hits 65923007 # ITB hits
|
|
|
|
|
system.cpu.itb.misses 38 # ITB misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 256667 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 4174.217956 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2174.217956 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1071384000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 256667 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 558050000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 256667 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 217111 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4357.993028 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.993028 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 30930 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 811375500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.857538 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 186181 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 439013500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.857538 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 186181 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 80592 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4188.374777 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2188.374777 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 337549500 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 80592 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 176365500 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 80592 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 334093 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_misses 334093 # number of Writeback misses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_misses 334093 # number of Writeback MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.avg_refs 4.206809 # Average number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 473778 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 4251.480192 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2251.480192 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 30930 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 1882759500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.934716 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 442848 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 997063500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.934716 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 442848 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 473778 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 4251.480192 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2251.480192 # average overall mshr miss latency
|
2007-02-14 19:05:20 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.overall_hits 30930 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 1882759500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.934716 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 442848 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 997063500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.934716 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 442848 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.replacements 14218 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 15715 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 8150.643180 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 66110 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.numCycles 325063615 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 11040699 # Number of cycles rename is blocking
|
2006-12-05 01:07:00 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 31586100 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 150557156 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 290380 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 895272473 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 679363424 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 518606333 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 116560800 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 9747531 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 37157112 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 54751444 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 317 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 72001269 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 103 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
