gem5/SConscript

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# -*- mode:python -*-
# Copyright (c) 2004 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import sys
from os.path import isdir
# This file defines how to build a particular configuration of M5
# based on variable settings in the 'env' build environment.
# Import build environment variable from SConstruct.
Import('env')
###################################################
#
# Define needed sources.
#
###################################################
# Base sources used by all configurations.
base_sources = Split('''
arch/alpha/decoder.cc
arch/alpha/alpha_full_cpu_exec.cc
arch/alpha/fast_cpu_exec.cc
arch/alpha/simple_cpu_exec.cc
arch/alpha/inorder_cpu_exec.cc
arch/alpha/full_cpu_exec.cc
arch/alpha/faults.cc
arch/alpha/isa_traits.cc
Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes. SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-26 00:00:49 +01:00
arch/alpha/ooo_cpu_exec.cc
base/circlebuf.cc
base/copyright.cc
base/cprintf.cc
New and improved configuration mechanism. No more writing of wierd ini files. The ini files are still used as an intermediate step, but a sophisticated python library exists to help build them more easily. SConscript: add the new embedded file stuff remove all of the old object description junk base/inifile.cc: base/inifile.hh: get rid of findDefault and findAppend since they were the source of much evil. base/trace.cc: For now, if we don't have the dprintf_stream set up, dump to standard out. We probably want a command line option for this. dev/alpha_console.cc: PioDevice now takes a platform parameter. All PioDevices must have a pio_latency parameter. We stick a dummy parameter in here for now until we get rid of the builder stuff. dev/alpha_console.hh: don't need Platform anymore dev/baddev.cc: PioDevice now takes a platform parameter. All PioDevices must have a pio_latency parameter. We stick a dummy parameter in here for now until we get rid of the builder stuff. Same for the platform parameter, though we just pass the PioDevice a null parameter since it isn't used by this device and it's quicker. dev/baddev.hh: fix #include guards dev/etherlink.cc: rename parameters. dev/ethertap.cc: rename parameters dev/ide_ctrl.cc: All devices need an address even if it will get overwritten later. dev/ide_disk.cc: use an enum for the drive ID stuff. rename disk_delay -> delay Actually, I think that we should implement "cable select" and have the controller tell the drive what it is. dev/io_device.cc: dev/io_device.hh: All IO devices take a Platform * dev/ns_gige.cc: all devices need an io_bus. rename header_bus to io_bus We don't need stuff for the interrupt controller since it's all in the platform now. dev/ns_gige.hh: We don't need stuff for the interrupt controller now since it's all in the platform. dev/pciconfigall.cc: Pass a dummy NULL to the PioDevice for the platform since we don't need one. dev/pcidev.cc: Move a bunch of common functionality into the PciDev dev/platform.hh: remove unneeded code dev/tsunami.cc: remove unused param dev/tsunami_cchip.cc: pass platform pointer dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: pass platform variable dev/uart.hh: don't need to keep a platform pointer. it's in the base class kern/linux/linux_system.cc: kern/tru64/tru64_system.cc: rename some parameters sim/builder.cc: clean up builder code. use more parameters from the config node. all sections with a type= are now created, the old mechanisms no longer work sim/builder.hh: remove some extra variables since they are found in the ConfigNode sim/main.cc: add a quick hack command line argument -X to dump out the embedded files. (probably should be fixed up a little.) accept .mpy files printing to the streams has to happen after the hierarchy is built since we're moving away from param contexts sim/param.cc: add parsing support for ranges sim/process.cc: isValid isn't very useful anymore. interpret the names stdout, stderr, cout, cerr for the file descriptors sim/pyconfig/SConscript: Add Action handlers for creating an embedded python file and for creating an embedded C file. use these action handlers to embed all objects found in the objects tree into the binary along with the importer and the m5config stuff sim/pyconfig/m5config.py: Major changes to the original configuration file generator. These changes largely involve implementing copy-on-write like semantics for all of the SimObjects. Real documentation must be written. sim/universe.cc: Universe becomes a SimObject since we don't really have the notion of param contexts in the python code. --HG-- rename : sim/pyconfig/m5configbase.py => sim/pyconfig/m5config.py extra : convert_revision : c353453e5beb91c37f15755998fc0d8858c6829a
2005-01-15 10:12:25 +01:00
base/embedfile.cc
base/fast_alloc.cc
base/fifo_buffer.cc
base/hostinfo.cc
base/hybrid_pred.cc
base/inifile.cc
base/intmath.cc
base/match.cc
base/misc.cc
base/output.cc
base/pollevent.cc
base/python.cc
base/range.cc
base/random.cc
base/sat_counter.cc
base/socket.cc
base/statistics.cc
base/str.cc
base/time.cc
base/trace.cc
base/traceflags.cc
base/userinfo.cc
base/compression/lzss_compression.cc
base/loader/aout_object.cc
base/loader/ecoff_object.cc
base/loader/elf_object.cc
base/loader/object_file.cc
base/loader/symtab.cc
base/stats/events.cc
base/stats/python.cc
base/stats/statdb.cc
base/stats/visit.cc
base/stats/text.cc
cpu/base_cpu.cc
cpu/base_dyn_inst.cc
cpu/exec_context.cc
cpu/exetrace.cc
cpu/pc_event.cc
cpu/static_inst.cc
Update to make multiple instruction issue and different latencies work. Also change to ref counted DynInst. SConscript: Add branch predictor, BTB, load store queue, and storesets. arch/isa_parser.py: Specify the template parameter for AlphaDynInst base/traceflags.py: Add load store queue, store set, and mem dependence unit to the list of trace flags. cpu/base_dyn_inst.cc: Change formating, add in debug statement. cpu/base_dyn_inst.hh: Change DynInst to be RefCounted, add flag to clear whether or not this instruction can commit. This is likely to be removed in the future. cpu/beta_cpu/alpha_dyn_inst.cc: AlphaDynInst has been changed to be templated, so now this CC file is just used to force instantiations of AlphaDynInst. cpu/beta_cpu/alpha_dyn_inst.hh: Changed AlphaDynInst to be templated on Impl. Removed some unnecessary functions. cpu/beta_cpu/alpha_full_cpu.cc: AlphaFullCPU has been changed to be templated, so this CC file is now just used to force instantation of AlphaFullCPU. cpu/beta_cpu/alpha_full_cpu.hh: Change AlphaFullCPU to be templated on Impl. cpu/beta_cpu/alpha_impl.hh: Update it to reflect AlphaDynInst and AlphaFullCPU being templated on Impl. Also removed time buffers from here, as they are really a part of the CPU and are thus in the CPU policy now. cpu/beta_cpu/alpha_params.hh: Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't need to specifically declare any parameters that are already in the BaseFullCPU. cpu/beta_cpu/comm.hh: Changed the structure of the time buffer communication structs. Now they include the size of the packet of instructions it is sending. Added some parameters to the backwards communication struct, mainly for squashing. cpu/beta_cpu/commit.hh: Update typenames to reflect change in location of time buffer structs. Update DynInst to DynInstPtr (it is refcounted now). cpu/beta_cpu/commit_impl.hh: Formatting changes mainly. Also sends back proper information on branch mispredicts so that the bpred unit can update itself. Updated behavior for non-speculative instructions (stores, any other non-spec instructions): once they reach the head of the ROB, the ROB signals back to the IQ that it can go ahead and issue the non-speculative instruction. The instruction itself is updated so that commit won't try to commit it again until it is done executing. cpu/beta_cpu/cpu_policy.hh: Added branch prediction unit, mem dependence prediction unit, load store queue. Moved time buffer structs from AlphaSimpleImpl to here. cpu/beta_cpu/decode.hh: Changed typedefs to reflect change in location of time buffer structs and also the change from DynInst to ref counted DynInstPtr. cpu/beta_cpu/decode_impl.hh: Continues to buffer instructions even while unblocking now. Changed how it loops through groups of instructions so it can properly block during the middle of a group of instructions. cpu/beta_cpu/fetch.hh: Changed typedefs to reflect change in location of time buffer structs and the change to ref counted DynInsts. Also added in branch brediction unit. cpu/beta_cpu/fetch_impl.hh: Add in branch prediction. Changed how fetch checks inputs and its current state to make for easier logic. cpu/beta_cpu/free_list.cc: Changed int regs and float regs to logically use one flat namespace. Future change will be moving them to a single scoreboard to conserve space. cpu/beta_cpu/free_list.hh: Mostly debugging statements. Might be removed for performance in future. cpu/beta_cpu/full_cpu.cc: Added in some debugging statements. Updated BaseFullCPU to take a params object. cpu/beta_cpu/full_cpu.hh: Added params class within BaseCPU that other param classes will be able to inherit from. Updated typedefs to reflect change in location of time buffer structs and ref counted DynInst. cpu/beta_cpu/iew.hh: Updated typedefs to reflect change in location of time buffer structs and use of ref counted DynInsts. cpu/beta_cpu/iew_impl.hh: Added in load store queue, updated iew to be able to execute non- speculative instructions, instead of having them execute in commit. cpu/beta_cpu/inst_queue.hh: Updated change to ref counted DynInsts. Changed inst queue to hold non-speculative instructions as well, which are issued only when commit signals backwards that a nonspeculative instruction is at the head of the ROB. cpu/beta_cpu/inst_queue_impl.hh: Updated to allow for non-speculative instructions to be in the inst queue. Also added some debug functions. cpu/beta_cpu/regfile.hh: Added debugging statements, changed formatting. cpu/beta_cpu/rename.hh: Updated typedefs, added some functions to clean up code. cpu/beta_cpu/rename_impl.hh: Moved some code into functions to make it easier to read. cpu/beta_cpu/rename_map.cc: Changed int and float reg behavior to use a single flat namespace. In the future, the rename maps can be combined to a single rename map to save space. cpu/beta_cpu/rename_map.hh: Added destructor. cpu/beta_cpu/rob.hh: Updated it with change from DynInst to ref counted DynInst. cpu/beta_cpu/rob_impl.hh: Formatting, updated to use ref counted DynInst. cpu/static_inst.hh: Updated forward declaration for AlphaDynInst now that it is templated. --HG-- extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
2004-09-23 20:06:03 +02:00
cpu/beta_cpu/2bit_local_pred.cc
cpu/beta_cpu/alpha_dyn_inst.cc
cpu/beta_cpu/alpha_full_cpu.cc
Update to make multiple instruction issue and different latencies work. Also change to ref counted DynInst. SConscript: Add branch predictor, BTB, load store queue, and storesets. arch/isa_parser.py: Specify the template parameter for AlphaDynInst base/traceflags.py: Add load store queue, store set, and mem dependence unit to the list of trace flags. cpu/base_dyn_inst.cc: Change formating, add in debug statement. cpu/base_dyn_inst.hh: Change DynInst to be RefCounted, add flag to clear whether or not this instruction can commit. This is likely to be removed in the future. cpu/beta_cpu/alpha_dyn_inst.cc: AlphaDynInst has been changed to be templated, so now this CC file is just used to force instantiations of AlphaDynInst. cpu/beta_cpu/alpha_dyn_inst.hh: Changed AlphaDynInst to be templated on Impl. Removed some unnecessary functions. cpu/beta_cpu/alpha_full_cpu.cc: AlphaFullCPU has been changed to be templated, so this CC file is now just used to force instantation of AlphaFullCPU. cpu/beta_cpu/alpha_full_cpu.hh: Change AlphaFullCPU to be templated on Impl. cpu/beta_cpu/alpha_impl.hh: Update it to reflect AlphaDynInst and AlphaFullCPU being templated on Impl. Also removed time buffers from here, as they are really a part of the CPU and are thus in the CPU policy now. cpu/beta_cpu/alpha_params.hh: Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't need to specifically declare any parameters that are already in the BaseFullCPU. cpu/beta_cpu/comm.hh: Changed the structure of the time buffer communication structs. Now they include the size of the packet of instructions it is sending. Added some parameters to the backwards communication struct, mainly for squashing. cpu/beta_cpu/commit.hh: Update typenames to reflect change in location of time buffer structs. Update DynInst to DynInstPtr (it is refcounted now). cpu/beta_cpu/commit_impl.hh: Formatting changes mainly. Also sends back proper information on branch mispredicts so that the bpred unit can update itself. Updated behavior for non-speculative instructions (stores, any other non-spec instructions): once they reach the head of the ROB, the ROB signals back to the IQ that it can go ahead and issue the non-speculative instruction. The instruction itself is updated so that commit won't try to commit it again until it is done executing. cpu/beta_cpu/cpu_policy.hh: Added branch prediction unit, mem dependence prediction unit, load store queue. Moved time buffer structs from AlphaSimpleImpl to here. cpu/beta_cpu/decode.hh: Changed typedefs to reflect change in location of time buffer structs and also the change from DynInst to ref counted DynInstPtr. cpu/beta_cpu/decode_impl.hh: Continues to buffer instructions even while unblocking now. Changed how it loops through groups of instructions so it can properly block during the middle of a group of instructions. cpu/beta_cpu/fetch.hh: Changed typedefs to reflect change in location of time buffer structs and the change to ref counted DynInsts. Also added in branch brediction unit. cpu/beta_cpu/fetch_impl.hh: Add in branch prediction. Changed how fetch checks inputs and its current state to make for easier logic. cpu/beta_cpu/free_list.cc: Changed int regs and float regs to logically use one flat namespace. Future change will be moving them to a single scoreboard to conserve space. cpu/beta_cpu/free_list.hh: Mostly debugging statements. Might be removed for performance in future. cpu/beta_cpu/full_cpu.cc: Added in some debugging statements. Updated BaseFullCPU to take a params object. cpu/beta_cpu/full_cpu.hh: Added params class within BaseCPU that other param classes will be able to inherit from. Updated typedefs to reflect change in location of time buffer structs and ref counted DynInst. cpu/beta_cpu/iew.hh: Updated typedefs to reflect change in location of time buffer structs and use of ref counted DynInsts. cpu/beta_cpu/iew_impl.hh: Added in load store queue, updated iew to be able to execute non- speculative instructions, instead of having them execute in commit. cpu/beta_cpu/inst_queue.hh: Updated change to ref counted DynInsts. Changed inst queue to hold non-speculative instructions as well, which are issued only when commit signals backwards that a nonspeculative instruction is at the head of the ROB. cpu/beta_cpu/inst_queue_impl.hh: Updated to allow for non-speculative instructions to be in the inst queue. Also added some debug functions. cpu/beta_cpu/regfile.hh: Added debugging statements, changed formatting. cpu/beta_cpu/rename.hh: Updated typedefs, added some functions to clean up code. cpu/beta_cpu/rename_impl.hh: Moved some code into functions to make it easier to read. cpu/beta_cpu/rename_map.cc: Changed int and float reg behavior to use a single flat namespace. In the future, the rename maps can be combined to a single rename map to save space. cpu/beta_cpu/rename_map.hh: Added destructor. cpu/beta_cpu/rob.hh: Updated it with change from DynInst to ref counted DynInst. cpu/beta_cpu/rob_impl.hh: Formatting, updated to use ref counted DynInst. cpu/static_inst.hh: Updated forward declaration for AlphaDynInst now that it is templated. --HG-- extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
2004-09-23 20:06:03 +02:00
cpu/beta_cpu/alpha_full_cpu_builder.cc
cpu/beta_cpu/bpred_unit.cc
cpu/beta_cpu/btb.cc
cpu/beta_cpu/commit.cc
cpu/beta_cpu/decode.cc
cpu/beta_cpu/fetch.cc
cpu/beta_cpu/free_list.cc
cpu/beta_cpu/full_cpu.cc
cpu/beta_cpu/iew.cc
cpu/beta_cpu/inst_queue.cc
Update to make multiple instruction issue and different latencies work. Also change to ref counted DynInst. SConscript: Add branch predictor, BTB, load store queue, and storesets. arch/isa_parser.py: Specify the template parameter for AlphaDynInst base/traceflags.py: Add load store queue, store set, and mem dependence unit to the list of trace flags. cpu/base_dyn_inst.cc: Change formating, add in debug statement. cpu/base_dyn_inst.hh: Change DynInst to be RefCounted, add flag to clear whether or not this instruction can commit. This is likely to be removed in the future. cpu/beta_cpu/alpha_dyn_inst.cc: AlphaDynInst has been changed to be templated, so now this CC file is just used to force instantiations of AlphaDynInst. cpu/beta_cpu/alpha_dyn_inst.hh: Changed AlphaDynInst to be templated on Impl. Removed some unnecessary functions. cpu/beta_cpu/alpha_full_cpu.cc: AlphaFullCPU has been changed to be templated, so this CC file is now just used to force instantation of AlphaFullCPU. cpu/beta_cpu/alpha_full_cpu.hh: Change AlphaFullCPU to be templated on Impl. cpu/beta_cpu/alpha_impl.hh: Update it to reflect AlphaDynInst and AlphaFullCPU being templated on Impl. Also removed time buffers from here, as they are really a part of the CPU and are thus in the CPU policy now. cpu/beta_cpu/alpha_params.hh: Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't need to specifically declare any parameters that are already in the BaseFullCPU. cpu/beta_cpu/comm.hh: Changed the structure of the time buffer communication structs. Now they include the size of the packet of instructions it is sending. Added some parameters to the backwards communication struct, mainly for squashing. cpu/beta_cpu/commit.hh: Update typenames to reflect change in location of time buffer structs. Update DynInst to DynInstPtr (it is refcounted now). cpu/beta_cpu/commit_impl.hh: Formatting changes mainly. Also sends back proper information on branch mispredicts so that the bpred unit can update itself. Updated behavior for non-speculative instructions (stores, any other non-spec instructions): once they reach the head of the ROB, the ROB signals back to the IQ that it can go ahead and issue the non-speculative instruction. The instruction itself is updated so that commit won't try to commit it again until it is done executing. cpu/beta_cpu/cpu_policy.hh: Added branch prediction unit, mem dependence prediction unit, load store queue. Moved time buffer structs from AlphaSimpleImpl to here. cpu/beta_cpu/decode.hh: Changed typedefs to reflect change in location of time buffer structs and also the change from DynInst to ref counted DynInstPtr. cpu/beta_cpu/decode_impl.hh: Continues to buffer instructions even while unblocking now. Changed how it loops through groups of instructions so it can properly block during the middle of a group of instructions. cpu/beta_cpu/fetch.hh: Changed typedefs to reflect change in location of time buffer structs and the change to ref counted DynInsts. Also added in branch brediction unit. cpu/beta_cpu/fetch_impl.hh: Add in branch prediction. Changed how fetch checks inputs and its current state to make for easier logic. cpu/beta_cpu/free_list.cc: Changed int regs and float regs to logically use one flat namespace. Future change will be moving them to a single scoreboard to conserve space. cpu/beta_cpu/free_list.hh: Mostly debugging statements. Might be removed for performance in future. cpu/beta_cpu/full_cpu.cc: Added in some debugging statements. Updated BaseFullCPU to take a params object. cpu/beta_cpu/full_cpu.hh: Added params class within BaseCPU that other param classes will be able to inherit from. Updated typedefs to reflect change in location of time buffer structs and ref counted DynInst. cpu/beta_cpu/iew.hh: Updated typedefs to reflect change in location of time buffer structs and use of ref counted DynInsts. cpu/beta_cpu/iew_impl.hh: Added in load store queue, updated iew to be able to execute non- speculative instructions, instead of having them execute in commit. cpu/beta_cpu/inst_queue.hh: Updated change to ref counted DynInsts. Changed inst queue to hold non-speculative instructions as well, which are issued only when commit signals backwards that a nonspeculative instruction is at the head of the ROB. cpu/beta_cpu/inst_queue_impl.hh: Updated to allow for non-speculative instructions to be in the inst queue. Also added some debug functions. cpu/beta_cpu/regfile.hh: Added debugging statements, changed formatting. cpu/beta_cpu/rename.hh: Updated typedefs, added some functions to clean up code. cpu/beta_cpu/rename_impl.hh: Moved some code into functions to make it easier to read. cpu/beta_cpu/rename_map.cc: Changed int and float reg behavior to use a single flat namespace. In the future, the rename maps can be combined to a single rename map to save space. cpu/beta_cpu/rename_map.hh: Added destructor. cpu/beta_cpu/rob.hh: Updated it with change from DynInst to ref counted DynInst. cpu/beta_cpu/rob_impl.hh: Formatting, updated to use ref counted DynInst. cpu/static_inst.hh: Updated forward declaration for AlphaDynInst now that it is templated. --HG-- extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
2004-09-23 20:06:03 +02:00
cpu/beta_cpu/ldstq.cc
cpu/beta_cpu/mem_dep_unit.cc
Check in of various updates to the CPU. Mainly adds in stats, improves branch prediction, and makes memory dependence work properly. SConscript: Added return address stack, tournament predictor. cpu/base_cpu.cc: Added debug break and print statements. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Comment out possibly unneeded variables. cpu/beta_cpu/2bit_local_pred.cc: 2bit predictor no longer speculatively updates itself. cpu/beta_cpu/alpha_dyn_inst.hh: Comment formatting. cpu/beta_cpu/alpha_full_cpu.hh: Formatting cpu/beta_cpu/alpha_full_cpu_builder.cc: Added new parameters for branch predictors, and IQ parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Register stats. cpu/beta_cpu/alpha_params.hh: Added parameters for IQ, branch predictors, and store sets. cpu/beta_cpu/bpred_unit.cc: Removed one class. cpu/beta_cpu/bpred_unit.hh: Add in RAS, stats. Changed branch predictor unit functionality so that it holds a history of past branches so it can update, and also hold a proper history of the RAS so it can be restored on branch mispredicts. cpu/beta_cpu/bpred_unit_impl.hh: Added in stats, history of branches, RAS. Now bpred unit actually modifies the instruction's predicted next PC. cpu/beta_cpu/btb.cc: Add in sanity checks. cpu/beta_cpu/comm.hh: Add in communication where needed, remove it where it's not. cpu/beta_cpu/commit.hh: cpu/beta_cpu/rename.hh: cpu/beta_cpu/rename_impl.hh: Add in stats. cpu/beta_cpu/commit_impl.hh: Stats, update what is sent back on branch mispredict. cpu/beta_cpu/cpu_policy.hh: Change the bpred unit being used. cpu/beta_cpu/decode.hh: cpu/beta_cpu/decode_impl.hh: Stats. cpu/beta_cpu/fetch.hh: Stats, change squash so it can handle squashes from decode differently than squashes from commit. cpu/beta_cpu/fetch_impl.hh: Add in stats. Change how a cache line is fetched. Update to work with caches. Also have separate functions for different behavior if squash is coming from decode vs commit. cpu/beta_cpu/free_list.hh: Remove some old comments. cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/full_cpu.hh: Added function to remove instructions from back of instruction list until a certain sequence number. cpu/beta_cpu/iew.hh: Stats, separate squashing behavior due to branches vs memory. cpu/beta_cpu/iew_impl.hh: Stats, separate squashing behavior for branches vs memory. cpu/beta_cpu/inst_queue.cc: Debug stuff cpu/beta_cpu/inst_queue.hh: Stats, change how mem dep unit works, debug stuff cpu/beta_cpu/inst_queue_impl.hh: Stats, change how mem dep unit works, debug stuff. Also add in parameters that used to be hardcoded. cpu/beta_cpu/mem_dep_unit.hh: cpu/beta_cpu/mem_dep_unit_impl.hh: Add in stats, change how memory dependence unit works. It now holds the memory instructions that are waiting for their memory dependences to resolve. It provides which instructions are ready directly to the IQ. cpu/beta_cpu/regfile.hh: Fix up sanity checks. cpu/beta_cpu/rename_map.cc: Fix loop variable type. cpu/beta_cpu/rob_impl.hh: Remove intermediate DynInstPtr cpu/beta_cpu/store_set.cc: Add in debugging statements. cpu/beta_cpu/store_set.hh: Reorder function arguments to match the rest of the calls. --HG-- extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
2004-10-22 00:02:36 +02:00
cpu/beta_cpu/ras.cc
cpu/beta_cpu/rename.cc
cpu/beta_cpu/rename_map.cc
cpu/beta_cpu/rob.cc
Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes. SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-26 00:00:49 +01:00
cpu/beta_cpu/sat_counter.cc
Update to make multiple instruction issue and different latencies work. Also change to ref counted DynInst. SConscript: Add branch predictor, BTB, load store queue, and storesets. arch/isa_parser.py: Specify the template parameter for AlphaDynInst base/traceflags.py: Add load store queue, store set, and mem dependence unit to the list of trace flags. cpu/base_dyn_inst.cc: Change formating, add in debug statement. cpu/base_dyn_inst.hh: Change DynInst to be RefCounted, add flag to clear whether or not this instruction can commit. This is likely to be removed in the future. cpu/beta_cpu/alpha_dyn_inst.cc: AlphaDynInst has been changed to be templated, so now this CC file is just used to force instantiations of AlphaDynInst. cpu/beta_cpu/alpha_dyn_inst.hh: Changed AlphaDynInst to be templated on Impl. Removed some unnecessary functions. cpu/beta_cpu/alpha_full_cpu.cc: AlphaFullCPU has been changed to be templated, so this CC file is now just used to force instantation of AlphaFullCPU. cpu/beta_cpu/alpha_full_cpu.hh: Change AlphaFullCPU to be templated on Impl. cpu/beta_cpu/alpha_impl.hh: Update it to reflect AlphaDynInst and AlphaFullCPU being templated on Impl. Also removed time buffers from here, as they are really a part of the CPU and are thus in the CPU policy now. cpu/beta_cpu/alpha_params.hh: Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't need to specifically declare any parameters that are already in the BaseFullCPU. cpu/beta_cpu/comm.hh: Changed the structure of the time buffer communication structs. Now they include the size of the packet of instructions it is sending. Added some parameters to the backwards communication struct, mainly for squashing. cpu/beta_cpu/commit.hh: Update typenames to reflect change in location of time buffer structs. Update DynInst to DynInstPtr (it is refcounted now). cpu/beta_cpu/commit_impl.hh: Formatting changes mainly. Also sends back proper information on branch mispredicts so that the bpred unit can update itself. Updated behavior for non-speculative instructions (stores, any other non-spec instructions): once they reach the head of the ROB, the ROB signals back to the IQ that it can go ahead and issue the non-speculative instruction. The instruction itself is updated so that commit won't try to commit it again until it is done executing. cpu/beta_cpu/cpu_policy.hh: Added branch prediction unit, mem dependence prediction unit, load store queue. Moved time buffer structs from AlphaSimpleImpl to here. cpu/beta_cpu/decode.hh: Changed typedefs to reflect change in location of time buffer structs and also the change from DynInst to ref counted DynInstPtr. cpu/beta_cpu/decode_impl.hh: Continues to buffer instructions even while unblocking now. Changed how it loops through groups of instructions so it can properly block during the middle of a group of instructions. cpu/beta_cpu/fetch.hh: Changed typedefs to reflect change in location of time buffer structs and the change to ref counted DynInsts. Also added in branch brediction unit. cpu/beta_cpu/fetch_impl.hh: Add in branch prediction. Changed how fetch checks inputs and its current state to make for easier logic. cpu/beta_cpu/free_list.cc: Changed int regs and float regs to logically use one flat namespace. Future change will be moving them to a single scoreboard to conserve space. cpu/beta_cpu/free_list.hh: Mostly debugging statements. Might be removed for performance in future. cpu/beta_cpu/full_cpu.cc: Added in some debugging statements. Updated BaseFullCPU to take a params object. cpu/beta_cpu/full_cpu.hh: Added params class within BaseCPU that other param classes will be able to inherit from. Updated typedefs to reflect change in location of time buffer structs and ref counted DynInst. cpu/beta_cpu/iew.hh: Updated typedefs to reflect change in location of time buffer structs and use of ref counted DynInsts. cpu/beta_cpu/iew_impl.hh: Added in load store queue, updated iew to be able to execute non- speculative instructions, instead of having them execute in commit. cpu/beta_cpu/inst_queue.hh: Updated change to ref counted DynInsts. Changed inst queue to hold non-speculative instructions as well, which are issued only when commit signals backwards that a nonspeculative instruction is at the head of the ROB. cpu/beta_cpu/inst_queue_impl.hh: Updated to allow for non-speculative instructions to be in the inst queue. Also added some debug functions. cpu/beta_cpu/regfile.hh: Added debugging statements, changed formatting. cpu/beta_cpu/rename.hh: Updated typedefs, added some functions to clean up code. cpu/beta_cpu/rename_impl.hh: Moved some code into functions to make it easier to read. cpu/beta_cpu/rename_map.cc: Changed int and float reg behavior to use a single flat namespace. In the future, the rename maps can be combined to a single rename map to save space. cpu/beta_cpu/rename_map.hh: Added destructor. cpu/beta_cpu/rob.hh: Updated it with change from DynInst to ref counted DynInst. cpu/beta_cpu/rob_impl.hh: Formatting, updated to use ref counted DynInst. cpu/static_inst.hh: Updated forward declaration for AlphaDynInst now that it is templated. --HG-- extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
2004-09-23 20:06:03 +02:00
cpu/beta_cpu/store_set.cc
Check in of various updates to the CPU. Mainly adds in stats, improves branch prediction, and makes memory dependence work properly. SConscript: Added return address stack, tournament predictor. cpu/base_cpu.cc: Added debug break and print statements. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Comment out possibly unneeded variables. cpu/beta_cpu/2bit_local_pred.cc: 2bit predictor no longer speculatively updates itself. cpu/beta_cpu/alpha_dyn_inst.hh: Comment formatting. cpu/beta_cpu/alpha_full_cpu.hh: Formatting cpu/beta_cpu/alpha_full_cpu_builder.cc: Added new parameters for branch predictors, and IQ parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Register stats. cpu/beta_cpu/alpha_params.hh: Added parameters for IQ, branch predictors, and store sets. cpu/beta_cpu/bpred_unit.cc: Removed one class. cpu/beta_cpu/bpred_unit.hh: Add in RAS, stats. Changed branch predictor unit functionality so that it holds a history of past branches so it can update, and also hold a proper history of the RAS so it can be restored on branch mispredicts. cpu/beta_cpu/bpred_unit_impl.hh: Added in stats, history of branches, RAS. Now bpred unit actually modifies the instruction's predicted next PC. cpu/beta_cpu/btb.cc: Add in sanity checks. cpu/beta_cpu/comm.hh: Add in communication where needed, remove it where it's not. cpu/beta_cpu/commit.hh: cpu/beta_cpu/rename.hh: cpu/beta_cpu/rename_impl.hh: Add in stats. cpu/beta_cpu/commit_impl.hh: Stats, update what is sent back on branch mispredict. cpu/beta_cpu/cpu_policy.hh: Change the bpred unit being used. cpu/beta_cpu/decode.hh: cpu/beta_cpu/decode_impl.hh: Stats. cpu/beta_cpu/fetch.hh: Stats, change squash so it can handle squashes from decode differently than squashes from commit. cpu/beta_cpu/fetch_impl.hh: Add in stats. Change how a cache line is fetched. Update to work with caches. Also have separate functions for different behavior if squash is coming from decode vs commit. cpu/beta_cpu/free_list.hh: Remove some old comments. cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/full_cpu.hh: Added function to remove instructions from back of instruction list until a certain sequence number. cpu/beta_cpu/iew.hh: Stats, separate squashing behavior due to branches vs memory. cpu/beta_cpu/iew_impl.hh: Stats, separate squashing behavior for branches vs memory. cpu/beta_cpu/inst_queue.cc: Debug stuff cpu/beta_cpu/inst_queue.hh: Stats, change how mem dep unit works, debug stuff cpu/beta_cpu/inst_queue_impl.hh: Stats, change how mem dep unit works, debug stuff. Also add in parameters that used to be hardcoded. cpu/beta_cpu/mem_dep_unit.hh: cpu/beta_cpu/mem_dep_unit_impl.hh: Add in stats, change how memory dependence unit works. It now holds the memory instructions that are waiting for their memory dependences to resolve. It provides which instructions are ready directly to the IQ. cpu/beta_cpu/regfile.hh: Fix up sanity checks. cpu/beta_cpu/rename_map.cc: Fix loop variable type. cpu/beta_cpu/rob_impl.hh: Remove intermediate DynInstPtr cpu/beta_cpu/store_set.cc: Add in debugging statements. cpu/beta_cpu/store_set.hh: Reorder function arguments to match the rest of the calls. --HG-- extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
2004-10-22 00:02:36 +02:00
cpu/beta_cpu/tournament_pred.cc
cpu/fast_cpu/fast_cpu.cc
cpu/full_cpu/bpred.cc
cpu/full_cpu/commit.cc
cpu/full_cpu/create_vector.cc
cpu/full_cpu/cv_spec_state.cc
cpu/full_cpu/dd_queue.cc
cpu/full_cpu/dep_link.cc
cpu/full_cpu/dispatch.cc
cpu/full_cpu/dyn_inst.cc
cpu/full_cpu/execute.cc
cpu/full_cpu/fetch.cc
cpu/full_cpu/floss_reasons.cc
cpu/full_cpu/fu_pool.cc
cpu/full_cpu/full_cpu.cc
cpu/full_cpu/inst_fifo.cc
cpu/full_cpu/instpipe.cc
cpu/full_cpu/issue.cc
cpu/full_cpu/ls_queue.cc
cpu/full_cpu/machine_queue.cc
cpu/full_cpu/pc_sample_profile.cc
Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes. SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-26 00:00:49 +01:00
cpu/full_cpu/pipetrace.cc
cpu/full_cpu/readyq.cc
cpu/full_cpu/reg_info.cc
cpu/full_cpu/rob_station.cc
cpu/full_cpu/spec_memory.cc
cpu/full_cpu/spec_state.cc
cpu/full_cpu/storebuffer.cc
cpu/full_cpu/writeback.cc
cpu/full_cpu/iq/iq_station.cc
cpu/full_cpu/iq/iqueue.cc
cpu/full_cpu/iq/segmented/chain_info.cc
cpu/full_cpu/iq/segmented/chain_wire.cc
cpu/full_cpu/iq/segmented/iq_seg.cc
cpu/full_cpu/iq/segmented/iq_segmented.cc
cpu/full_cpu/iq/segmented/seg_chain.cc
cpu/full_cpu/iq/seznec/iq_seznec.cc
cpu/full_cpu/iq/standard/iq_standard.cc
cpu/inorder_cpu/inorder_cpu.cc
cpu/ooo_cpu/ea_list.cc
cpu/ooo_cpu/ooo_cpu.cc
cpu/ooo_cpu/ooo_dyn_inst.cc
cpu/ooo_cpu/ooo_sim_obj.cc
cpu/sampling_cpu/sampling_cpu.cc
cpu/simple_cpu/simple_cpu.cc
cpu/trace/reader/mem_trace_reader.cc
cpu/trace/reader/ibm_reader.cc
cpu/trace/reader/itx_reader.cc
cpu/trace/reader/m5_reader.cc
mem/base_hier.cc
mem/base_mem.cc
mem/hier_params.cc
mem/mem_cmd.cc
mem/mem_debug.cc
mem/mem_req.cc
mem/memory_interface.cc
mem/bus/base_interface.cc
mem/bus/bus.cc
mem/bus/bus_bridge.cc
mem/bus/bus_bridge_master.cc
mem/bus/bus_bridge_slave.cc
mem/bus/bus_interface.cc
mem/bus/dma_bus_interface.cc
mem/bus/dma_interface.cc
mem/bus/master_interface.cc
mem/bus/slave_interface.cc
mem/cache/base_cache.cc
mem/cache/cache.cc
mem/cache/cache_builder.cc
mem/cache/coherence/coherence_protocol.cc
mem/cache/coherence/uni_coherence.cc
mem/cache/miss/blocking_buffer.cc
mem/cache/miss/miss_queue.cc
mem/cache/miss/mshr.cc
mem/cache/miss/mshr_queue.cc
mem/cache/prefetch/base_prefetcher.cc
mem/cache/prefetch/ghb_prefetcher.cc
mem/cache/prefetch/prefetcher.cc
mem/cache/prefetch/stride_prefetcher.cc
mem/cache/prefetch/tagged_prefetcher.cc
mem/cache/tags/base_tags.cc
mem/cache/tags/cache_tags.cc
mem/cache/tags/fa_lru.cc
mem/cache/tags/iic.cc
mem/cache/tags/lru.cc
mem/cache/tags/split.cc
mem/cache/tags/split_lifo.cc
mem/cache/tags/split_lru.cc
mem/cache/tags/repl/gen.cc
mem/cache/tags/repl/repl.cc
mem/functional_mem/functional_memory.cc
mem/functional_mem/main_memory.cc
mem/timing_mem/base_memory.cc
mem/timing_mem/memory_builder.cc
mem/timing_mem/simple_mem_bank.cc
mem/trace/itx_writer.cc
mem/trace/mem_trace_writer.cc
mem/trace/m5_writer.cc
stick all python stuff into a top level python directory. create an m5 package in python/m5 move the objects package into the m5 package move the m5config into the m5 package as config leave both importers outside of the package. SConscript: sim/main.cc: move sim/pyconfig/* -> python python/SConscript: m5config.py -> m5/config.py (now automatically embedded) objects -> python/m5/objects embed all python files in python/m5 python/m5/config.py: importer renamed mpy_importer move code to m5/__init__.py test/genini.py: deal with new python organization keep track of paths we want to add and add them after parameters are parsed. --HG-- rename : sim/pyconfig/SConscript => python/SConscript rename : sim/pyconfig/m5config.py => python/m5/config.py rename : objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.mpy rename : objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.mpy rename : objects/BadDevice.mpy => python/m5/objects/BadDevice.mpy rename : objects/BaseCPU.mpy => python/m5/objects/BaseCPU.mpy rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy rename : objects/BaseSystem.mpy => python/m5/objects/BaseSystem.mpy rename : objects/Bus.mpy => python/m5/objects/Bus.mpy rename : objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.mpy rename : objects/Device.mpy => python/m5/objects/Device.mpy rename : objects/DiskImage.mpy => python/m5/objects/DiskImage.mpy rename : objects/Ethernet.mpy => python/m5/objects/Ethernet.mpy rename : objects/Ide.mpy => python/m5/objects/Ide.mpy rename : objects/IntrControl.mpy => python/m5/objects/IntrControl.mpy rename : objects/MemTest.mpy => python/m5/objects/MemTest.mpy rename : objects/Pci.mpy => python/m5/objects/Pci.mpy rename : objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.mpy rename : objects/Platform.mpy => python/m5/objects/Platform.mpy rename : objects/Process.mpy => python/m5/objects/Process.mpy rename : objects/Repl.mpy => python/m5/objects/Repl.mpy rename : objects/Root.mpy => python/m5/objects/Root.mpy rename : objects/SimConsole.mpy => python/m5/objects/SimConsole.mpy rename : objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.mpy rename : objects/Tsunami.mpy => python/m5/objects/Tsunami.mpy rename : objects/Uart.mpy => python/m5/objects/Uart.mpy extra : convert_revision : aebf6ccda33028b1125974ca8b6aeab6f7570f30
2005-03-12 00:28:38 +01:00
python/pyconfig.cc
python/embedded_py.cc
sim/builder.cc
sim/configfile.cc
sim/debug.cc
sim/eventq.cc
sim/main.cc
sim/param.cc
sim/profile.cc
sim/serialize.cc
sim/sim_events.cc
sim/sim_exit.cc
sim/sim_object.cc
sim/startup.cc
sim/stat_context.cc
sim/stat_control.cc
sim/trace_context.cc
sim/universe.cc
''')
# MySql sources
mysql_sources = Split('''
base/mysql.cc
base/stats/mysql.cc
''')
# Full-system sources
full_system_sources = Split('''
arch/alpha/alpha_memory.cc
arch/alpha/arguments.cc
arch/alpha/ev5.cc
arch/alpha/osfpal.cc
arch/alpha/pseudo_inst.cc
arch/alpha/vtophys.cc
Clean up network header stuff and make it more generic. Use libdnet when we can instead of our own home grown stuff. SConscript: separate the crc code into its own file base/inet.cc: move the crc stuff to crc.cc add generic code for calculating ip/tcp/udp checksums base/inet.hh: - move crc stuff to crc.hh - #include all of the libdnet stuff. (this makes base/inet.hh the only file you need to include if you want to use this kind of stuff.) - Wrap some of the libdnet structs to get easier access to structure members. These wrappers will automatically deal with masking/shifting/ byte-swapping. base/refcnt.hh: If one derives from RefCountingPtr, they should have access to the internal data pointer. build/SConstruct: make #include of dnet stuff work dev/etherlink.cc: dev/ethertap.cc: dev/ethertap.hh: EtherPacket -> PacketData dev/etherpkt.cc: EtherPacket -> PacketData add a function for populating extra info about a packet. Basically just gives pointers to ethernet/ip/tcp/udp headers if they exist. dev/etherpkt.hh: EtherPacket -> PacketData remove most of the packet header stuff from teh PacketData class and just add a few generic functions for grabbing various headers that may exist in the packet. The old functionality is contained in the headers. dev/ns_gige.cc: - IP -> Ip, UDP -> Udp, TCP ->Tcp when used in variable names - get rid of our own byte swapping functions. - whack checksum code and use libdnet version. - Get pointers to the various packet headers and grab info from those headers. (The byte swapping in the headers now.) - Add stats for Udp Checksums dev/ns_gige.hh: use libdnet for checksum code. IP -> Ip, TCP -> Tcp in variable names add stats for UDP checksums --HG-- extra : convert_revision : 96c4160e1967b7c0090acd456df4a76e1f3aab53
2004-09-20 16:43:53 +02:00
base/crc.cc
base/inet.cc
base/remote_gdb.cc
cpu/intr_control.cc
dev/alpha_console.cc
dev/baddev.cc
dev/simconsole.cc
dev/disk_image.cc
dev/dma.cc
dev/etherbus.cc
dev/etherdump.cc
dev/etherint.cc
dev/etherlink.cc
dev/etherpkt.cc
dev/ethertap.cc
dev/ide_ctrl.cc
dev/ide_disk.cc
dev/io_device.cc
dev/ns_gige.cc
dev/etherdev.cc
dev/pciconfigall.cc
dev/pcidev.cc
dev/pktfifo.cc
dev/scsi.cc
dev/scsi_ctrl.cc
dev/scsi_disk.cc
dev/scsi_none.cc
dev/sinic.cc
dev/simple_disk.cc
dev/tlaser_clock.cc
dev/tlaser_ipi.cc
dev/tlaser_mbox.cc
dev/tlaser_mc146818.cc
dev/tlaser_node.cc
dev/tlaser_pcia.cc
dev/tlaser_pcidev.cc
dev/tlaser_serial.cc
dev/turbolaser.cc
dev/tsunami.cc
dev/tsunami_cchip.cc
dev/tsunami_fake.cc
dev/tsunami_io.cc
dev/tsunami_pchip.cc
dev/uart.cc
- Clean up and factor out all of the binning code into a single place so it's easier to work with. - Add support for binning kernel/user/idle time separately from lisa's binning stuff, but make the two compatible. - KernelStats used to directly implement the pImpl idiom, but it makes more sense to just remove the level of indirection and make the exec context have a pointer to the stats. - Factor common code out of LinuxSystem and Tru64System and put it into the System base class. While doing that, make all constructors take a pointer to a parameter struct instead of naming the parameters individually to make it much easier to add parameters to these classes. SConscript: Move the function tracking and binning stuff around. arch/alpha/ev5.cc: kernelStats is now a pointer arch/alpha/pseudo_inst.cc: kernelStats is now a pointer the parameters to the system have been moved into their own struct base/trace.hh: provide a little functor class for wrapping a string that can allow you to define name() in any scope very simply for use with DPRINTF cpu/base_cpu.cc: New order of arguments for consistency. cpu/exec_context.cc: kernelStats no longer has the level of indirection in it, execContext has the indirection now. so, kernelStats is a pointer. We also need a pointer to the kernelBinning stuff from the system and we need to figure out if we want to do binning or not. Move a whole bunch of code into kern_binning.cc so it's all in the same place. cpu/exec_context.hh: We want pointers to the kernel binning/stats stuff and we'll have the exec_context and system have the level of indirection instead of having the extra layer in the kernel stats class. cpu/simple_cpu/simple_cpu.cc: call through the exec context to do the special binning stuff. kern/kernel_stats.cc: kern/kernel_stats.hh: Re-organize the stats stuff and remove the level of indirection (that was there to simplify building) and move the binning stuff into its own class/file. kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/system.cc: sim/system.hh: move lots of common system code into the base system class so that it can be shared between linux, tru64, and whatever else we decide to support in the future. Make the constructor take a pointer to a parameter struct so that it is easier to pass parameters to the parent. kern/system_events.cc: move the majority of the binning code into the Kernel::Binning class in the kern_binning file kern/system_events.hh: FnEvents only need to know the bin create the Idle start event to find the PCBB of the idle process when it starts. kern/tru64/tru64_events.cc: memCtrl -> memctrl sim/process.cc: sim/process.hh: re-order args for consistency --HG-- extra : convert_revision : 86cb39738c41fcd680f2aad125c9dde000227b2b
2004-08-20 17:35:31 +02:00
kern/kernel_binning.cc
kern/kernel_stats.cc
kern/system_events.cc
kern/linux/linux_events.cc
kern/linux/linux_syscalls.cc
kern/linux/linux_system.cc
kern/linux/printk.cc
kern/tru64/dump_mbuf.cc
kern/tru64/printf.cc
kern/tru64/tru64_events.cc
kern/tru64/tru64_syscalls.cc
kern/tru64/tru64_system.cc
mem/functional_mem/memory_control.cc
mem/functional_mem/physical_memory.cc
dev/platform.cc
sim/system.cc
''')
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
arch/alpha/alpha_common_syscall_emul.cc
arch/alpha/alpha_linux_process.cc
arch/alpha/alpha_tru64_process.cc
cpu/memtest/memtest.cc
cpu/trace/opt_cpu.cc
cpu/trace/trace_cpu.cc
eio/eio.cc
eio/exolex.cc
eio/libexo.cc
sim/process.cc
sim/syscall_emul.cc
''')
targetarch_files = Split('''
alpha_common_syscall_emul.hh
alpha_linux_process.hh
alpha_memory.hh
alpha_tru64_process.hh
aout_machdep.h
arguments.hh
byte_swap.hh
ecoff_machdep.h
elf_machdep.h
ev5.hh
faults.hh
isa_fullsys_traits.hh
isa_traits.hh
machine_exo.h
osfpal.hh
pseudo_inst.hh
vptr.hh
vtophys.hh
''')
for f in targetarch_files:
env.Command('targetarch/' + f, 'arch/alpha/' + f,
'''echo '#include "arch/alpha/%s"' > $TARGET''' % f)
# Set up complete list of sources based on configuration.
sources = base_sources
if env['FULL_SYSTEM']:
sources += full_system_sources
else:
sources += syscall_emulation_sources
extra_libraries = []
env.Append(LIBS=['z'])
if isdir('/usr/lib64/mysql') or isdir('/usr/lib/mysql') or \
isdir('/usr/local/lib/mysql'):
print 'Compiling with MySQL support!'
env.Append(LIBPATH=['/usr/lib64/mysql', '/usr/local/lib/mysql/',
'/usr/lib/mysql'])
env.Append(CPPPATH=['/usr/local/include/mysql', '/usr/include/mysql'])
sources += mysql_sources
env.Append(CPPDEFINES = 'USE_MYSQL')
env.Append(CPPDEFINES = 'STATS_BINNING')
env.Append(LIBS=['mysqlclient'])
###################################################
#
# Special build rules.
#
###################################################
# base/traceflags.{cc,hh} are generated from base/traceflags.py.
# $TARGET.base will expand to "<build-dir>/base/traceflags".
env.Command(Split('base/traceflags.hh base/traceflags.cc'),
'base/traceflags.py',
'python $SOURCE $TARGET.base')
# several files are generated from arch/$TARGET_ISA/isa_desc.
env.Command(Split('''arch/alpha/decoder.cc
arch/alpha/decoder.hh
arch/alpha/alpha_full_cpu_exec.cc
arch/alpha/fast_cpu_exec.cc
arch/alpha/simple_cpu_exec.cc
arch/alpha/inorder_cpu_exec.cc
Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes. SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-26 00:00:49 +01:00
arch/alpha/full_cpu_exec.cc
arch/alpha/ooo_cpu_exec.cc'''),
Split('''arch/alpha/isa_desc
arch/isa_parser.py'''),
'$SRCDIR/arch/isa_parser.py $SOURCE $TARGET.dir arch/alpha')
# libelf build is described in its own SConscript file.
# SConscript-local is the per-config build, which just copies some
# header files into a place where they can be found.
SConscript('libelf/SConscript-local', exports = 'env', duplicate=0)
stick all python stuff into a top level python directory. create an m5 package in python/m5 move the objects package into the m5 package move the m5config into the m5 package as config leave both importers outside of the package. SConscript: sim/main.cc: move sim/pyconfig/* -> python python/SConscript: m5config.py -> m5/config.py (now automatically embedded) objects -> python/m5/objects embed all python files in python/m5 python/m5/config.py: importer renamed mpy_importer move code to m5/__init__.py test/genini.py: deal with new python organization keep track of paths we want to add and add them after parameters are parsed. --HG-- rename : sim/pyconfig/SConscript => python/SConscript rename : sim/pyconfig/m5config.py => python/m5/config.py rename : objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.mpy rename : objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.mpy rename : objects/BadDevice.mpy => python/m5/objects/BadDevice.mpy rename : objects/BaseCPU.mpy => python/m5/objects/BaseCPU.mpy rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy rename : objects/BaseSystem.mpy => python/m5/objects/BaseSystem.mpy rename : objects/Bus.mpy => python/m5/objects/Bus.mpy rename : objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.mpy rename : objects/Device.mpy => python/m5/objects/Device.mpy rename : objects/DiskImage.mpy => python/m5/objects/DiskImage.mpy rename : objects/Ethernet.mpy => python/m5/objects/Ethernet.mpy rename : objects/Ide.mpy => python/m5/objects/Ide.mpy rename : objects/IntrControl.mpy => python/m5/objects/IntrControl.mpy rename : objects/MemTest.mpy => python/m5/objects/MemTest.mpy rename : objects/Pci.mpy => python/m5/objects/Pci.mpy rename : objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.mpy rename : objects/Platform.mpy => python/m5/objects/Platform.mpy rename : objects/Process.mpy => python/m5/objects/Process.mpy rename : objects/Repl.mpy => python/m5/objects/Repl.mpy rename : objects/Root.mpy => python/m5/objects/Root.mpy rename : objects/SimConsole.mpy => python/m5/objects/SimConsole.mpy rename : objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.mpy rename : objects/Tsunami.mpy => python/m5/objects/Tsunami.mpy rename : objects/Uart.mpy => python/m5/objects/Uart.mpy extra : convert_revision : aebf6ccda33028b1125974ca8b6aeab6f7570f30
2005-03-12 00:28:38 +01:00
SConscript('python/SConscript', exports = ['env'], duplicate=0)
SConscript('simobj/SConscript', exports = 'env', duplicate=0)
# This function adds the specified sources to the given build
# environment, and returns a list of all the corresponding SCons
# Object nodes (including an extra one for date.cc). We explicitly
# add the Object nodes so we can set up special dependencies for
# date.cc.
def make_objs(sources, env):
objs = [env.Object(s) for s in sources]
# make date.cc depend on all other objects so it always gets
# recompiled whenever anything else does
date_obj = env.Object('base/date.cc')
env.Depends(date_obj, objs)
objs.append(date_obj)
objs.extend(extra_libraries)
return objs
###################################################
#
# Define binaries. Each different build type (debug, opt, etc.) gets
# a slightly different build environment.
#
###################################################
# Include file paths are rooted in this directory. SCons will
# automatically expand '.' to refer to both the source directory and
# the corresponding build directory to pick up generated include
# files.
env.Append(CPPPATH='.')
# Debug binary
debug = env.Copy(OBJSUFFIX='.do')
debug.Append(CCFLAGS=Split('-g -gstabs+ -O0'))
debug.Append(CPPDEFINES='DEBUG')
debug.Program(target = 'm5.debug', source = make_objs(sources, debug))
# Optimized binary
opt = env.Copy()
opt.Append(CCFLAGS=Split('-g -O5'))
opt.Program(target = 'm5.opt', source = make_objs(sources, opt))
# "Fast" binary
fast = env.Copy(OBJSUFFIX='.fo')
fast.Append(CCFLAGS=Split('-O5'))
fast.Append(CPPDEFINES='NDEBUG')
fast.Program(target = 'm5.fast.unstripped', source = make_objs(sources, fast))
fast.Command(target = 'm5.fast', source = 'm5.fast.unstripped',
action = 'strip $SOURCE -o $TARGET')
# Profiled binary
prof = env.Copy(OBJSUFFIX='.po')
prof.Append(CCFLAGS=Split('-O5 -g -pg'), LINKFLAGS='-pg')
prof.Program(target = 'm5.prof', source = make_objs(sources, prof))