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gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt

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ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
---------- Begin Simulation Statistics ----------
Ruby: Bump the stats after recent memory controller changes This patch simply bumps the stats to avoid having failing regressions. Someone with more insight in the changes should verify that these differences all make sense.
2012-09-10 17:57:47 +02:00
sim_seconds 0.000052 # Number of seconds simulated
sim_ticks 52498 # Number of ticks simulated
final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000 # Frequency of simulated ticks
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
host_inst_rate 24935 # Simulator instruction rate (inst/s)
host_op_rate 24932 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 507835 # Simulator tick rate (ticks/s)
host_mem_usage 124536 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_insts 2577 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 2577 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.ruby.clk_domain.clock 1 # Clock period in ticks
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 1248 # delay histogram for all message
system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 1248 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
system.ruby.outstanding_req_hist::samples 3295
system.ruby.outstanding_req_hist::mean 1
system.ruby.outstanding_req_hist::gmean 1
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist::total 3295
system.ruby.latency_hist::bucket_size 16
system.ruby.latency_hist::max_bucket 159
system.ruby.latency_hist::samples 3294
system.ruby.latency_hist::mean 14.937462
system.ruby.latency_hist::gmean 5.391229
system.ruby.latency_hist::stdev 24.804214
system.ruby.latency_hist | 2668 81.00% 81.00% | 0 0.00% 81.00% | 0 0.00% 81.00% | 142 4.31% 85.31% | 448 13.60% 98.91% | 36 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist::total 3294
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
system.ruby.hit_latency_hist::samples 2668
system.ruby.hit_latency_hist::mean 3
system.ruby.hit_latency_hist::gmean 3.000000
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist::total 2668
system.ruby.miss_latency_hist::bucket_size 16
system.ruby.miss_latency_hist::max_bucket 159
system.ruby.miss_latency_hist::samples 626
system.ruby.miss_latency_hist::mean 65.814696
system.ruby.miss_latency_hist::gmean 65.560981
system.ruby.miss_latency_hist::stdev 6.377524
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 142 22.68% 22.68% | 448 71.57% 94.25% | 36 5.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist::total 626
system.ruby.Directory.incomplete_times 625
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
stats: updates statistics for ruby regressions
2013-05-21 18:32:57 +02:00
system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers0.percent_links_utilized 5.943084
system.ruby.network.routers0.msg_count.Control::2 626
system.ruby.network.routers0.msg_count.Data::2 622
system.ruby.network.routers0.msg_count.Response_Data::4 626
system.ruby.network.routers0.msg_count.Writeback_Control::3 622
system.ruby.network.routers0.msg_bytes.Control::2 5008
system.ruby.network.routers0.msg_bytes.Data::2 44784
system.ruby.network.routers0.msg_bytes.Response_Data::4 45072
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976
stats: updates due to changes to ruby Ruby's controller statistics have been mostly moved to stats.txt now. Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are also being updated.
2013-06-10 13:46:20 +02:00
system.ruby.dir_cntrl0.memBuffer.memReq 1248 # Total number of memory requests
system.ruby.dir_cntrl0.memBuffer.memRead 626 # Number of memory reads
system.ruby.dir_cntrl0.memBuffer.memWrite 622 # Number of memory writes
system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 915 # Delay stalled at the head of the bank queue
system.ruby.dir_cntrl0.memBuffer.totalStalls 915 # Total number of stall cycles
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.733173 # Expected number of stall cycles per request
system.ruby.dir_cntrl0.memBuffer.memBankBusy 352 # memory stalls due to busy bank
system.ruby.dir_cntrl0.memBuffer.memBusBusy 497 # memory stalls due to busy bus
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 26 # memory stalls due to read write turnaround
system.ruby.dir_cntrl0.memBuffer.memArbWait 40 # memory stalls due to arbitration
system.ruby.dir_cntrl0.memBuffer.memBankCount | 55 4.41% 4.41% | 40 3.21% 7.61% | 0 0.00% 7.61% | 100 8.01% 15.62% | 42 3.37% 18.99% | 42 3.37% 22.36% | 88 7.05% 29.41% | 45 3.61% 33.01% | 14 1.12% 34.13% | 10 0.80% 34.94% | 14 1.12% 36.06% | 10 0.80% 36.86% | 46 3.69% 40.54% | 82 6.57% 47.12% | 38 3.04% 50.16% | 6 0.48% 50.64% | 22 1.76% 52.40% | 14 1.12% 53.53% | 14 1.12% 54.65% | 48 3.85% 58.49% | 20 1.60% 60.10% | 52 4.17% 64.26% | 26 2.08% 66.35% | 92 7.37% 73.72% | 34 2.72% 76.44% | 10 0.80% 77.24% | 12 0.96% 78.21% | 24 1.92% 80.13% | 28 2.24% 82.37% | 44 3.53% 85.90% | 38 3.04% 88.94% | 138 11.06% 100.00% # Number of accesses per bank
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1248 # Number of accesses per bank
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers1.percent_links_utilized 5.943084
system.ruby.network.routers1.msg_count.Control::2 626
system.ruby.network.routers1.msg_count.Data::2 622
system.ruby.network.routers1.msg_count.Response_Data::4 626
system.ruby.network.routers1.msg_count.Writeback_Control::3 622
system.ruby.network.routers1.msg_bytes.Control::2 5008
system.ruby.network.routers1.msg_bytes.Data::2 44784
system.ruby.network.routers1.msg_bytes.Response_Data::4 45072
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976
system.ruby.network.routers2.percent_links_utilized 5.943084
system.ruby.network.routers2.msg_count.Control::2 626
system.ruby.network.routers2.msg_count.Data::2 622
system.ruby.network.routers2.msg_count.Response_Data::4 626
system.ruby.network.routers2.msg_count.Writeback_Control::3 622
system.ruby.network.routers2.msg_bytes.Control::2 5008
system.ruby.network.routers2.msg_bytes.Data::2 44784
system.ruby.network.routers2.msg_bytes.Response_Data::4 45072
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.ruby.network.msg_count.Control 1878
system.ruby.network.msg_count.Data 1866
system.ruby.network.msg_count.Response_Data 1878
system.ruby.network.msg_count.Writeback_Control 1866
system.ruby.network.msg_byte.Control 15024
system.ruby.network.msg_byte.Data 134352
system.ruby.network.msg_byte.Response_Data 135216
system.ruby.network.msg_byte.Writeback_Control 14928
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.clk_domain.clock 1 # Clock period in ticks
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 419 # DTB read accesses
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.data_hits 709 # DTB hits
system.cpu.dtb.data_misses 8 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 717 # DTB accesses
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.itb.fetch_hits 2586 # ITB hits
system.cpu.itb.fetch_misses 11 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2597 # ITB accesses
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
Ruby: Bump the stats after recent memory controller changes This patch simply bumps the stats to avoid having failing regressions. Someone with more insight in the changes should verify that these differences all make sense.
2012-09-10 17:57:47 +02:00
system.cpu.numCycles 52498 # number of cpu cycles simulated
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedInsts 2577 # Number of instructions committed
system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.num_int_insts 2375 # number of integer instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_insts 6 # number of float instructions
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.num_mem_refs 717 # number of memory refs
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_load_insts 419 # Number of load instructions
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.num_store_insts 298 # Number of store instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_idle_cycles 0 # Number of idle cycles
Ruby: Bump the stats after recent memory controller changes This patch simply bumps the stats to avoid having failing regressions. Someone with more insight in the changes should verify that these differences all make sense.
2012-09-10 17:57:47 +02:00
system.cpu.num_busy_cycles 52498 # Number of busy cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers0.throttle0.link_utilization 5.958322
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976
system.ruby.network.routers0.throttle1.link_utilization 5.927845
system.ruby.network.routers0.throttle1.msg_count.Control::2 626
system.ruby.network.routers0.throttle1.msg_count.Data::2 622
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784
system.ruby.network.routers1.throttle0.link_utilization 5.927845
system.ruby.network.routers1.throttle0.msg_count.Control::2 626
system.ruby.network.routers1.throttle0.msg_count.Data::2 622
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784
system.ruby.network.routers1.throttle1.link_utilization 5.958322
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976
system.ruby.network.routers2.throttle0.link_utilization 5.958322
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976
system.ruby.network.routers2.throttle1.link_utilization 5.927845
system.ruby.network.routers2.throttle1.msg_count.Control::2 626
system.ruby.network.routers2.throttle1.msg_count.Data::2 622
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 44784
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 626 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 626 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 626 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2
system.ruby.LD.latency_hist::bucket_size 16
system.ruby.LD.latency_hist::max_bucket 159
system.ruby.LD.latency_hist::samples 415
system.ruby.LD.latency_hist::mean 40.332530
system.ruby.LD.latency_hist::gmean 18.593767
system.ruby.LD.latency_hist::stdev 31.596647
system.ruby.LD.latency_hist | 170 40.96% 40.96% | 0 0.00% 40.96% | 0 0.00% 40.96% | 49 11.81% 52.77% | 178 42.89% 95.66% | 18 4.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist::total 415
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
system.ruby.LD.hit_latency_hist::samples 170
system.ruby.LD.hit_latency_hist::mean 3
system.ruby.LD.hit_latency_hist::gmean 3.000000
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist::total 170
system.ruby.LD.miss_latency_hist::bucket_size 16
system.ruby.LD.miss_latency_hist::max_bucket 159
system.ruby.LD.miss_latency_hist::samples 245
system.ruby.LD.miss_latency_hist::mean 66.236735
system.ruby.LD.miss_latency_hist::gmean 65.930929
system.ruby.LD.miss_latency_hist::stdev 7.007686
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 20.00% 20.00% | 178 72.65% 92.65% | 18 7.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist::total 245
system.ruby.ST.latency_hist::bucket_size 16
system.ruby.ST.latency_hist::max_bucket 159
system.ruby.ST.latency_hist::samples 294
system.ruby.ST.latency_hist::mean 20.945578
system.ruby.ST.latency_hist::gmean 7.241284
system.ruby.ST.latency_hist::stdev 28.634041
system.ruby.ST.latency_hist | 210 71.43% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 17 5.78% 77.21% | 62 21.09% 98.30% | 5 1.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist::total 294
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
system.ruby.ST.hit_latency_hist::samples 210
system.ruby.ST.hit_latency_hist::mean 3
system.ruby.ST.hit_latency_hist::gmean 3.000000
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist::total 210
system.ruby.ST.miss_latency_hist::bucket_size 16
system.ruby.ST.miss_latency_hist::max_bucket 159
system.ruby.ST.miss_latency_hist::samples 84
system.ruby.ST.miss_latency_hist::mean 65.809524
system.ruby.ST.miss_latency_hist::gmean 65.546776
system.ruby.ST.miss_latency_hist::stdev 6.522392
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 20.24% 20.24% | 62 73.81% 94.05% | 5 5.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist::total 84
system.ruby.IFETCH.latency_hist::bucket_size 16
system.ruby.IFETCH.latency_hist::max_bucket 159
system.ruby.IFETCH.latency_hist::samples 2585
system.ruby.IFETCH.latency_hist::mean 10.177176
system.ruby.IFETCH.latency_hist::gmean 4.273616
system.ruby.IFETCH.latency_hist::stdev 20.019716
system.ruby.IFETCH.latency_hist | 2288 88.51% 88.51% | 0 0.00% 88.51% | 0 0.00% 88.51% | 76 2.94% 91.45% | 208 8.05% 99.50% | 13 0.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist::total 2585
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
system.ruby.IFETCH.hit_latency_hist::samples 2288
system.ruby.IFETCH.hit_latency_hist::mean 3
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist::total 2288
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
system.ruby.IFETCH.miss_latency_hist::samples 297
system.ruby.IFETCH.miss_latency_hist::mean 65.468013
system.ruby.IFETCH.miss_latency_hist::gmean 65.261366
system.ruby.IFETCH.miss_latency_hist::stdev 5.762163
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 76 25.59% 25.59% | 208 70.03% 95.62% | 13 4.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist::total 297
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
system.ruby.Directory.miss_mach_latency_hist::samples 626
system.ruby.Directory.miss_mach_latency_hist::mean 65.814696
system.ruby.Directory.miss_mach_latency_hist::gmean 65.560981
system.ruby.Directory.miss_mach_latency_hist::stdev 6.377524
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 142 22.68% 22.68% | 448 71.57% 94.25% | 36 5.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist::total 626
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan
system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9
system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan
system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9
system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 245
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 66.236735
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.930929
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 7.007686
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 20.00% 20.00% | 178 72.65% 92.65% | 18 7.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 245
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 84
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.809524
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.546776
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.522392
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 20.24% 20.24% | 62 73.81% 94.05% | 5 5.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 84
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 297
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.468013
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 65.261366
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 5.762163
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 76 25.59% 25.59% | 208 70.03% 95.62% | 13 4.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297
system.ruby.L1Cache_Controller.Load 415 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 294 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 626 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 622 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 622 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 245 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 297 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 84 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 170 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 2288 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 210 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 622 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 622 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 542 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 84 0.00% 0.00%
system.ruby.Directory_Controller.GETX 626 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 622 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00%
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink