2006-06-23 00:05:12 +02:00
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/*
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2013-07-18 14:31:16 +02:00
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* Copyright (c) 2011,2013 ARM Limited
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2012-01-31 16:46:03 +01:00
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2006-06-23 00:05:12 +02:00
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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2012-01-31 16:46:03 +01:00
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* Geoffrey Blake
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2006-06-23 00:05:12 +02:00
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*/
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#include <list>
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#include <string>
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2015-02-11 16:23:27 +01:00
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#include "arch/generic/tlb.hh"
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2011-11-18 10:33:28 +01:00
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#include "arch/kernel_stats.hh"
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#include "arch/vtophys.hh"
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2006-06-23 00:05:12 +02:00
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#include "cpu/checker/cpu.hh"
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2011-04-15 19:44:06 +02:00
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#include "cpu/base.hh"
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2006-06-23 00:05:12 +02:00
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#include "cpu/simple_thread.hh"
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#include "cpu/static_inst.hh"
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2006-10-20 08:38:45 +02:00
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#include "cpu/thread_context.hh"
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2012-01-31 16:46:03 +01:00
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#include "params/CheckerCPU.hh"
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2012-03-09 15:59:27 +01:00
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#include "sim/full_system.hh"
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2006-06-23 00:05:12 +02:00
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using namespace std;
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2012-01-31 16:46:03 +01:00
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using namespace TheISA;
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2006-06-23 00:05:12 +02:00
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void
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CheckerCPU::init()
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{
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2012-02-12 23:07:38 +01:00
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masterId = systemPtr->getMasterId(name());
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2006-06-23 00:05:12 +02:00
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}
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CheckerCPU::CheckerCPU(Params *p)
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2012-08-28 20:30:24 +02:00
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: BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
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tc(NULL), thread(NULL)
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2006-06-23 00:05:12 +02:00
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{
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memReq = NULL;
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2012-01-31 16:46:03 +01:00
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curStaticInst = NULL;
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curMacroStaticInst = NULL;
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2006-06-23 00:05:12 +02:00
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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youngestSN = 0;
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2014-01-24 22:29:30 +01:00
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changedPC = willChangePC = false;
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2006-06-23 00:05:12 +02:00
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exitOnError = p->exitOnError;
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warnOnlyOnLoadError = p->warnOnlyOnLoadError;
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itb = p->itb;
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dtb = p->dtb;
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2012-01-31 16:46:03 +01:00
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workload = p->workload;
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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updateOnError = true;
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2006-06-23 00:05:12 +02:00
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}
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CheckerCPU::~CheckerCPU()
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{
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}
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void
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CheckerCPU::setSystem(System *system)
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{
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2013-01-07 19:05:35 +01:00
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const Params *p(dynamic_cast<const Params *>(_params));
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2006-06-23 00:05:12 +02:00
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systemPtr = system;
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2012-03-09 15:59:27 +01:00
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if (FullSystem) {
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2013-01-07 19:05:35 +01:00
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thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
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p->isa[0], false);
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2012-03-09 15:59:27 +01:00
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} else {
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thread = new SimpleThread(this, 0, systemPtr,
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workload.size() ? workload[0] : NULL,
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2013-01-07 19:05:35 +01:00
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itb, dtb, p->isa[0]);
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2012-03-09 15:59:27 +01:00
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}
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2006-06-23 00:05:12 +02:00
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tc = thread->getTC();
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threadContexts.push_back(tc);
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thread->kernelStats = NULL;
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2012-03-09 15:59:27 +01:00
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// Thread should never be null after this
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assert(thread != NULL);
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2006-06-23 00:05:12 +02:00
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}
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void
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2013-03-26 19:46:42 +01:00
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CheckerCPU::setIcachePort(MasterPort *icache_port)
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2006-06-23 00:05:12 +02:00
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{
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icachePort = icache_port;
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}
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void
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2013-03-26 19:46:42 +01:00
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CheckerCPU::setDcachePort(MasterPort *dcache_port)
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2006-06-23 00:05:12 +02:00
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{
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dcachePort = dcache_port;
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}
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void
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2015-07-07 10:51:03 +02:00
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CheckerCPU::serialize(ostream &os) const
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2006-06-23 00:05:12 +02:00
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{
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}
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void
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2015-07-07 10:51:03 +02:00
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CheckerCPU::unserialize(CheckpointIn &cp)
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2006-06-23 00:05:12 +02:00
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{
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}
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Fault
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2012-01-31 16:46:03 +01:00
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CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
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2006-06-23 00:05:12 +02:00
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{
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2012-01-31 16:46:03 +01:00
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Fault fault = NoFault;
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int fullSize = size;
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2013-07-18 14:31:16 +02:00
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Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
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2012-01-31 16:46:03 +01:00
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bool checked_flags = false;
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bool flags_match = true;
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Addr pAddr = 0x0;
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if (secondAddr > addr)
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size = secondAddr - addr;
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// Need to account for multiple accesses like the Atomic and TimingSimple
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while (1) {
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2015-01-22 11:00:53 +01:00
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memReq = new Request(0, addr, size, flags, masterId,
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2016-04-07 16:30:20 +02:00
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thread->pcState().instAddr(), tc->contextId());
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2012-01-31 16:46:03 +01:00
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// translate to physical address
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fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
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if (!checked_flags && fault == NoFault && unverifiedReq) {
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flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
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memReq->getPaddr(), memReq->getFlags());
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pAddr = memReq->getPaddr();
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checked_flags = true;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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// Now do the access
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if (fault == NoFault &&
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!memReq->getFlags().isSet(Request::NO_ACCESS)) {
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2014-05-13 19:20:48 +02:00
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PacketPtr pkt = Packet::createRead(memReq);
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2012-01-31 16:46:03 +01:00
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pkt->dataStatic(data);
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if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
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// Access memory to see if we have the same data
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dcachePort->sendFunctional(pkt);
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} else {
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// Assume the data is correct if it's an uncached access
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memcpy(data, unverifiedMemData, size);
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}
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delete memReq;
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memReq = NULL;
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delete pkt;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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if (fault != NoFault) {
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if (memReq->isPrefetch()) {
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fault = NoFault;
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}
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delete memReq;
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memReq = NULL;
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break;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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if (memReq != NULL) {
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delete memReq;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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//If we don't need to access a second cache line, stop now.
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if (secondAddr <= addr)
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{
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break;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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// Setup for accessing next cache line
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data += size;
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unverifiedMemData += size;
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size = addr + fullSize - secondAddr;
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addr = secondAddr;
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2006-06-23 00:05:12 +02:00
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}
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2012-01-31 16:46:03 +01:00
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if (!flags_match) {
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warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
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curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
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unverifiedReq->getFlags(), addr, pAddr, flags);
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handleError();
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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return fault;
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2006-06-23 00:05:12 +02:00
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}
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Fault
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2012-01-31 16:46:03 +01:00
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CheckerCPU::writeMem(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res)
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2006-06-23 00:05:12 +02:00
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{
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2012-01-31 16:46:03 +01:00
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Fault fault = NoFault;
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bool checked_flags = false;
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bool flags_match = true;
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Addr pAddr = 0x0;
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2014-10-30 05:18:24 +01:00
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static uint8_t zero_data[64] = {};
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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int fullSize = size;
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2006-06-23 00:05:12 +02:00
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2013-07-18 14:31:16 +02:00
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Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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if (secondAddr > addr)
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size = secondAddr - addr;
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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// Need to account for a multiple access like Atomic and Timing CPUs
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while (1) {
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2015-01-22 11:00:53 +01:00
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memReq = new Request(0, addr, size, flags, masterId,
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2016-04-07 16:30:20 +02:00
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thread->pcState().instAddr(), tc->contextId());
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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// translate to physical address
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fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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if (!checked_flags && fault == NoFault && unverifiedReq) {
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flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
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memReq->getPaddr(), memReq->getFlags());
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pAddr = memReq->getPaddr();
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checked_flags = true;
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2006-06-23 00:05:12 +02:00
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}
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2012-01-31 16:46:03 +01:00
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/*
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* We don't actually check memory for the store because there
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* is no guarantee it has left the lsq yet, and therefore we
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* can't verify the memory on stores without lsq snooping
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* enabled. This is left as future work for the Checker: LSQ snooping
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* and memory validation after stores have committed.
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*/
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2012-05-11 01:04:27 +02:00
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bool was_prefetch = memReq->isPrefetch();
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2012-01-31 16:46:03 +01:00
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delete memReq;
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//If we don't need to access a second cache line, stop now.
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if (fault != NoFault || secondAddr <= addr)
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{
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2012-05-11 01:04:27 +02:00
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if (fault != NoFault && was_prefetch) {
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2012-01-31 16:46:03 +01:00
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fault = NoFault;
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}
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break;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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//Update size and access address
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size = addr + fullSize - secondAddr;
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//And access the right address.
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addr = secondAddr;
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}
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if (!flags_match) {
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warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
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curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
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unverifiedReq->getFlags(), addr, pAddr, flags);
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handleError();
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}
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// Assume the result was the same as the one passed in. This checker
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// doesn't check if the SC should succeed or fail, it just checks the
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// value.
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if (unverifiedReq && res && unverifiedReq->extraDataValid())
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*res = unverifiedReq->getExtraData();
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// Entire purpose here is to make sure we are getting the
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// same data to send to the mem system as the CPU did.
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// Cannot check this is actually what went to memory because
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// there stores can be in ld/st queue or coherent operations
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// overwriting values.
|
2014-09-27 15:08:34 +02:00
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bool extraData = false;
|
2012-01-31 16:46:03 +01:00
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if (unverifiedReq) {
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extraData = unverifiedReq->extraDataValid() ?
|
2014-09-27 15:08:34 +02:00
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unverifiedReq->getExtraData() : true;
|
2012-01-31 16:46:03 +01:00
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}
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2014-10-30 05:18:24 +01:00
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// If the request is to ZERO a cache block, there is no data to check
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// against, but it's all zero. We need something to compare to, so use a
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// const set of zeros.
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if (flags & Request::CACHE_BLOCK_ZERO) {
|
|
|
|
assert(!data);
|
|
|
|
assert(sizeof(zero_data) <= fullSize);
|
|
|
|
data = zero_data;
|
|
|
|
}
|
|
|
|
|
2012-01-31 16:46:03 +01:00
|
|
|
if (unverifiedReq && unverifiedMemData &&
|
|
|
|
memcmp(data, unverifiedMemData, fullSize) && extraData) {
|
2014-09-12 16:22:47 +02:00
|
|
|
warn("%lli: Store value does not match value sent to memory! "
|
|
|
|
"data: %#x inst_data: %#x", curTick(), data,
|
2012-01-31 16:46:03 +01:00
|
|
|
unverifiedMemData);
|
|
|
|
handleError();
|
|
|
|
}
|
|
|
|
|
|
|
|
return fault;
|
2006-06-23 00:05:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
Addr
|
|
|
|
CheckerCPU::dbg_vtophys(Addr addr)
|
|
|
|
{
|
|
|
|
return vtophys(tc, addr);
|
|
|
|
}
|
|
|
|
|
2012-01-31 16:46:03 +01:00
|
|
|
/**
|
|
|
|
* Checks if the flags set by the Checker and Checkee match.
|
|
|
|
*/
|
2006-06-23 00:05:12 +02:00
|
|
|
bool
|
2012-01-31 16:46:03 +01:00
|
|
|
CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
|
|
|
|
Addr pAddr, int flags)
|
2006-06-23 00:05:12 +02:00
|
|
|
{
|
2012-01-31 16:46:03 +01:00
|
|
|
Addr unverifiedVAddr = unverified_req->getVaddr();
|
|
|
|
Addr unverifiedPAddr = unverified_req->getPaddr();
|
|
|
|
int unverifiedFlags = unverified_req->getFlags();
|
|
|
|
|
|
|
|
if (unverifiedVAddr != vAddr ||
|
|
|
|
unverifiedPAddr != pAddr ||
|
|
|
|
unverifiedFlags != flags) {
|
2006-06-23 00:05:12 +02:00
|
|
|
return false;
|
|
|
|
}
|
2012-01-31 16:46:03 +01:00
|
|
|
|
|
|
|
return true;
|
2006-06-23 00:05:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
CheckerCPU::dumpAndExit()
|
|
|
|
{
|
2012-01-31 16:46:03 +01:00
|
|
|
warn("%lli: Checker PC:%s",
|
|
|
|
curTick(), thread->pcState());
|
2006-06-23 00:05:12 +02:00
|
|
|
panic("Checker found an error!");
|
|
|
|
}
|