2006-06-23 00:05:12 +02:00
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/*
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2012-01-31 16:46:03 +01:00
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* Copyright (c) 2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2006-06-23 00:05:12 +02:00
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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2012-01-31 16:46:03 +01:00
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* Geoffrey Blake
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2006-06-23 00:05:12 +02:00
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*/
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#include <list>
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#include <string>
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2011-11-18 10:33:28 +01:00
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#include "arch/kernel_stats.hh"
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#include "arch/vtophys.hh"
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2006-06-23 00:05:12 +02:00
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#include "cpu/checker/cpu.hh"
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2011-04-15 19:44:06 +02:00
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#include "cpu/base.hh"
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2006-06-23 00:05:12 +02:00
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#include "cpu/simple_thread.hh"
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#include "cpu/static_inst.hh"
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2006-10-20 08:38:45 +02:00
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#include "cpu/thread_context.hh"
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2012-01-31 16:46:03 +01:00
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#include "params/CheckerCPU.hh"
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2012-03-09 15:59:27 +01:00
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#include "sim/full_system.hh"
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2012-01-31 16:46:03 +01:00
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#include "sim/tlb.hh"
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2006-06-23 00:05:12 +02:00
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using namespace std;
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2012-01-31 16:46:03 +01:00
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using namespace TheISA;
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2006-06-23 00:05:12 +02:00
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void
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CheckerCPU::init()
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{
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2012-02-12 23:07:38 +01:00
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masterId = systemPtr->getMasterId(name());
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2006-06-23 00:05:12 +02:00
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}
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CheckerCPU::CheckerCPU(Params *p)
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2012-03-02 15:21:48 +01:00
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: BaseCPU(p, true), thread(NULL), tc(NULL)
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2006-06-23 00:05:12 +02:00
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{
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memReq = NULL;
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2012-01-31 16:46:03 +01:00
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curStaticInst = NULL;
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curMacroStaticInst = NULL;
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2006-06-23 00:05:12 +02:00
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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youngestSN = 0;
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changedPC = willChangePC = changedNextPC = false;
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exitOnError = p->exitOnError;
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warnOnlyOnLoadError = p->warnOnlyOnLoadError;
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itb = p->itb;
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dtb = p->dtb;
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systemPtr = NULL;
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2012-01-31 16:46:03 +01:00
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workload = p->workload;
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2012-03-09 15:59:27 +01:00
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thread = NULL;
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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updateOnError = true;
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2006-06-23 00:05:12 +02:00
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}
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CheckerCPU::~CheckerCPU()
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{
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}
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void
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CheckerCPU::setSystem(System *system)
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{
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systemPtr = system;
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2012-03-09 15:59:27 +01:00
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if (FullSystem) {
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thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
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} else {
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thread = new SimpleThread(this, 0, systemPtr,
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workload.size() ? workload[0] : NULL,
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itb, dtb);
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}
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2006-06-23 00:05:12 +02:00
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tc = thread->getTC();
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threadContexts.push_back(tc);
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thread->kernelStats = NULL;
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2012-03-09 15:59:27 +01:00
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// Thread should never be null after this
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assert(thread != NULL);
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2006-06-23 00:05:12 +02:00
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}
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void
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2012-03-09 15:59:27 +01:00
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CheckerCPU::setIcachePort(CpuPort *icache_port)
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2006-06-23 00:05:12 +02:00
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{
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icachePort = icache_port;
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}
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void
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2012-03-09 15:59:27 +01:00
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CheckerCPU::setDcachePort(CpuPort *dcache_port)
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2006-06-23 00:05:12 +02:00
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{
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dcachePort = dcache_port;
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}
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void
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CheckerCPU::serialize(ostream &os)
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{
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}
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void
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CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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}
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Fault
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2012-01-31 16:46:03 +01:00
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CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
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2006-06-23 00:05:12 +02:00
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{
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2012-01-31 16:46:03 +01:00
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Fault fault = NoFault;
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unsigned blockSize = dcachePort->peerBlockSize();
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int fullSize = size;
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Addr secondAddr = roundDown(addr + size - 1, blockSize);
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bool checked_flags = false;
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bool flags_match = true;
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Addr pAddr = 0x0;
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if (secondAddr > addr)
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size = secondAddr - addr;
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// Need to account for multiple accesses like the Atomic and TimingSimple
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while (1) {
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memReq = new Request();
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2012-03-09 15:59:27 +01:00
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memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
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2012-01-31 16:46:03 +01:00
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// translate to physical address
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fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
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if (!checked_flags && fault == NoFault && unverifiedReq) {
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flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
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memReq->getPaddr(), memReq->getFlags());
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pAddr = memReq->getPaddr();
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checked_flags = true;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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// Now do the access
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if (fault == NoFault &&
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!memReq->getFlags().isSet(Request::NO_ACCESS)) {
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PacketPtr pkt = new Packet(memReq,
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MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
2012-04-14 11:45:55 +02:00
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memReq->isLLSC() ?
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MemCmd::LoadLockedReq :
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MemCmd::ReadReq);
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2012-01-31 16:46:03 +01:00
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pkt->dataStatic(data);
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if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
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// Access memory to see if we have the same data
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dcachePort->sendFunctional(pkt);
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} else {
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// Assume the data is correct if it's an uncached access
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memcpy(data, unverifiedMemData, size);
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}
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delete memReq;
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memReq = NULL;
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delete pkt;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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if (fault != NoFault) {
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if (memReq->isPrefetch()) {
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fault = NoFault;
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}
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delete memReq;
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memReq = NULL;
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break;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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if (memReq != NULL) {
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delete memReq;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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//If we don't need to access a second cache line, stop now.
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if (secondAddr <= addr)
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{
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break;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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// Setup for accessing next cache line
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data += size;
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unverifiedMemData += size;
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size = addr + fullSize - secondAddr;
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addr = secondAddr;
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2006-06-23 00:05:12 +02:00
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}
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2012-01-31 16:46:03 +01:00
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if (!flags_match) {
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warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
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curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
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unverifiedReq->getFlags(), addr, pAddr, flags);
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handleError();
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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return fault;
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2006-06-23 00:05:12 +02:00
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}
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Fault
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2012-01-31 16:46:03 +01:00
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CheckerCPU::writeMem(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res)
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2006-06-23 00:05:12 +02:00
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{
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2012-01-31 16:46:03 +01:00
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Fault fault = NoFault;
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bool checked_flags = false;
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bool flags_match = true;
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Addr pAddr = 0x0;
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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unsigned blockSize = dcachePort->peerBlockSize();
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int fullSize = size;
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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Addr secondAddr = roundDown(addr + size - 1, blockSize);
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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if (secondAddr > addr)
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size = secondAddr - addr;
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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// Need to account for a multiple access like Atomic and Timing CPUs
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while (1) {
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memReq = new Request();
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2012-02-12 23:07:38 +01:00
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memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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// translate to physical address
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fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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if (!checked_flags && fault == NoFault && unverifiedReq) {
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flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
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memReq->getPaddr(), memReq->getFlags());
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pAddr = memReq->getPaddr();
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checked_flags = true;
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2006-06-23 00:05:12 +02:00
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}
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2012-01-31 16:46:03 +01:00
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/*
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* We don't actually check memory for the store because there
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* is no guarantee it has left the lsq yet, and therefore we
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* can't verify the memory on stores without lsq snooping
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* enabled. This is left as future work for the Checker: LSQ snooping
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* and memory validation after stores have committed.
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*/
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delete memReq;
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//If we don't need to access a second cache line, stop now.
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if (fault != NoFault || secondAddr <= addr)
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{
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if (fault != NoFault && memReq->isPrefetch()) {
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fault = NoFault;
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}
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break;
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}
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2006-06-23 00:05:12 +02:00
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2012-01-31 16:46:03 +01:00
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//Update size and access address
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size = addr + fullSize - secondAddr;
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//And access the right address.
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addr = secondAddr;
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}
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if (!flags_match) {
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warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
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curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
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unverifiedReq->getFlags(), addr, pAddr, flags);
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handleError();
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}
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// Assume the result was the same as the one passed in. This checker
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// doesn't check if the SC should succeed or fail, it just checks the
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// value.
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if (unverifiedReq && res && unverifiedReq->extraDataValid())
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*res = unverifiedReq->getExtraData();
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// Entire purpose here is to make sure we are getting the
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// same data to send to the mem system as the CPU did.
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// Cannot check this is actually what went to memory because
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// there stores can be in ld/st queue or coherent operations
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// overwriting values.
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bool extraData;
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if (unverifiedReq) {
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extraData = unverifiedReq->extraDataValid() ?
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|
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unverifiedReq->getExtraData() : 1;
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}
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if (unverifiedReq && unverifiedMemData &&
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memcmp(data, unverifiedMemData, fullSize) && extraData) {
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warn("%lli: Store value does not match value sent to memory!\
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|
data: %#x inst_data: %#x", curTick(), data,
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|
|
unverifiedMemData);
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handleError();
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|
|
|
}
|
|
|
|
|
|
|
|
return fault;
|
2006-06-23 00:05:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
Addr
|
|
|
|
CheckerCPU::dbg_vtophys(Addr addr)
|
|
|
|
{
|
|
|
|
return vtophys(tc, addr);
|
|
|
|
}
|
|
|
|
|
2012-01-31 16:46:03 +01:00
|
|
|
/**
|
|
|
|
* Checks if the flags set by the Checker and Checkee match.
|
|
|
|
*/
|
2006-06-23 00:05:12 +02:00
|
|
|
bool
|
2012-01-31 16:46:03 +01:00
|
|
|
CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
|
|
|
|
Addr pAddr, int flags)
|
2006-06-23 00:05:12 +02:00
|
|
|
{
|
2012-01-31 16:46:03 +01:00
|
|
|
Addr unverifiedVAddr = unverified_req->getVaddr();
|
|
|
|
Addr unverifiedPAddr = unverified_req->getPaddr();
|
|
|
|
int unverifiedFlags = unverified_req->getFlags();
|
|
|
|
|
|
|
|
if (unverifiedVAddr != vAddr ||
|
|
|
|
unverifiedPAddr != pAddr ||
|
|
|
|
unverifiedFlags != flags) {
|
2006-06-23 00:05:12 +02:00
|
|
|
return false;
|
|
|
|
}
|
2012-01-31 16:46:03 +01:00
|
|
|
|
|
|
|
return true;
|
2006-06-23 00:05:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
CheckerCPU::dumpAndExit()
|
|
|
|
{
|
2012-01-31 16:46:03 +01:00
|
|
|
warn("%lli: Checker PC:%s",
|
|
|
|
curTick(), thread->pcState());
|
2006-06-23 00:05:12 +02:00
|
|
|
panic("Checker found an error!");
|
|
|
|
}
|