2006-07-27 23:47:43 +02:00
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|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2012-10-25 19:15:59 +02:00
|
|
|
sim_seconds 1.950814 # Number of seconds simulated
|
|
|
|
|
sim_ticks 1950813955500 # Number of ticks simulated
|
|
|
|
|
final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2012-01-25 18:19:50 +01:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2012-10-25 19:15:59 +02:00
|
|
|
host_inst_rate 770652 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_op_rate 770652 # Simulator op (including micro ops) rate (op/s)
|
|
|
|
|
host_tick_rate 24652738853 # Simulator tick rate (ticks/s)
|
2012-10-25 19:14:42 +02:00
|
|
|
host_mem_usage 325660 # Number of bytes of host memory used
|
2012-10-25 19:15:59 +02:00
|
|
|
host_seconds 79.13 # Real time elapsed on the host
|
|
|
|
|
sim_insts 60983017 # Number of instructions simulated
|
|
|
|
|
sim_ops 60983017 # Number of ops (including micro ops) simulated
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory
|
2012-10-15 14:12:21 +02:00
|
|
|
system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory
|
|
|
|
|
system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory
|
2012-10-15 14:12:21 +02:00
|
|
|
system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory
|
|
|
|
|
system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s)
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s)
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s)
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s)
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s)
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.readReqs 448191 # Total number of read requests seen
|
|
|
|
|
system.physmem.writeReqs 120414 # Total number of write requests seen
|
|
|
|
|
system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady
|
|
|
|
|
system.physmem.bytesRead 28684224 # Total number of bytes read from memory
|
|
|
|
|
system.physmem.bytesWritten 7706496 # Total number of bytes written to memory
|
|
|
|
|
system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize()
|
|
|
|
|
system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize()
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis
|
|
|
|
|
system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis
|
|
|
|
|
system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry
|
|
|
|
|
system.physmem.totGap 1950760240000 # Total gap between requests
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.readPktSize::6 448191 # Categorize read packet sizes
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
|
|
|
|
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.writePktSize::6 120944 # categorize write packet sizes
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
|
|
|
|
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.rdQLenPdf::0 409750 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::1 7530 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::2 5264 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::3 2349 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::4 2844 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::5 2407 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::6 1780 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::7 2013 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::8 1657 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::11 1572 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::12 1655 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::13 1735 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::14 1232 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::15 1426 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.wrQLenPdf::0 4348 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::1 4960 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::2 5066 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::3 5108 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::4 5181 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::6 5228 # What write queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::24 276 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays
|
|
|
|
|
system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests
|
|
|
|
|
system.physmem.totBusLat 1792536000 # Total cycles spent in databus access
|
|
|
|
|
system.physmem.totBankLat 6288996000 # Total cycles spent in bank access
|
|
|
|
|
system.physmem.avgQLat 6509.40 # Average queueing delay per request
|
|
|
|
|
system.physmem.avgBankLat 14033.74 # Average bank access latency per request
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.avgMemAccLat 24543.14 # Average memory access latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s
|
|
|
|
|
system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s
|
|
|
|
|
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
|
|
|
|
system.physmem.busUtil 0.12 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.avgRdQLen 0.01 # Average read queue length over time
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.avgWrQLen 10.51 # Average write queue length over time
|
|
|
|
|
system.physmem.readRowHits 428061 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 76773 # Number of row buffer hits during writes
|
|
|
|
|
system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.avgGap 3430782.78 # Average gap between requests
|
|
|
|
|
system.l2c.replacements 341335 # number of replacements
|
|
|
|
|
system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 2438054 # Total number of references to valid blocks.
|
|
|
|
|
system.l2c.sampled_refs 406311 # Sample count of references to valid blocks.
|
|
|
|
|
system.l2c.avg_refs 6.000463 # Average number of references to valid blocks.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit.
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.occ_blocks::writebacks 55545.332470 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.inst 4807.217204 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.data 4686.652945 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu1.inst 164.376424 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu1.data 43.456861 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_percent::writebacks 0.847555 # Average percentage of cache occupancy
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_hits::cpu0.inst 674205 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.data 658217 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.inst 328581 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.data 113535 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 1774538 # number of ReadReq hits
|
|
|
|
|
system.l2c.Writeback_hits::writebacks 791470 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 791470 # number of Writeback hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::total 738 # number of UpgradeReq hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::cpu0.data 123887 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::cpu1.data 48972 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::total 172859 # number of ReadExReq hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.inst 674205 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.data 782104 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.inst 328581 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.data 162507 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::total 1947397 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.inst 674205 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.data 782104 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.inst 328581 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.data 162507 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::total 1947397 # number of overall hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_misses::cpu0.inst 12926 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu0.data 271631 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu1.inst 612 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu1.data 247 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 285416 # number of ReadReq misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.UpgradeReq_misses::cpu0.data 2969 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1806 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::total 4775 # number of UpgradeReq misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 939 # number of SCUpgradeReq misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 944 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::total 1883 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::cpu0.data 115505 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::cpu1.data 6644 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 122149 # number of ReadExReq misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_misses::cpu0.inst 12926 # number of demand (read+write) misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_misses::cpu0.data 387136 # number of demand (read+write) misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_misses::cpu1.inst 612 # number of demand (read+write) misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_misses::cpu1.data 6891 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::total 407565 # number of demand (read+write) misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_misses::cpu0.inst 12926 # number of overall misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_misses::cpu0.data 387136 # number of overall misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_misses::cpu1.inst 612 # number of overall misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_misses::cpu1.data 6891 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::total 407565 # number of overall misses
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 706675500 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 11506519500 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 33342000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 15821000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::total 12262358000 # number of ReadReq miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 1244500 # number of UpgradeReq miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 10405997 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency::total 11650497 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 840000 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182000 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency::total 1022000 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 5700012000 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 427427500 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency::total 6127439500 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu0.inst 706675500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu0.data 17206531500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu1.inst 33342000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu1.data 443248500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::total 18389797500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu0.inst 706675500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu0.data 17206531500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu1.inst 33342000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu1.data 443248500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::total 18389797500 # number of overall miss cycles
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.inst 687131 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.data 929848 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.inst 329193 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.data 113782 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 2059954 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::writebacks 791470 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 791470 # number of Writeback accesses(hits+misses)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 3143 # number of UpgradeReq accesses(hits+misses)
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 2370 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 5513 # number of UpgradeReq accesses(hits+misses)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 975 # number of SCUpgradeReq accesses(hits+misses)
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 968 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::total 1943 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::cpu0.data 239392 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::cpu1.data 55616 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 295008 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.demand_accesses::cpu0.inst 687131 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.data 1169240 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.inst 329193 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.data 169398 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::total 2354962 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.inst 687131 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.data 1169240 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.inst 329193 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.data 169398 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::total 2354962 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.018812 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.292124 # miss rate for ReadReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.001859 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.002171 # miss rate for ReadReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_miss_rate::total 0.138555 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944639 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.762025 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::total 0.866135 # miss rate for UpgradeReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963077 # miss rate for SCUpgradeReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975207 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.969120 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.482493 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.119462 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::total 0.414053 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.018812 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.data 0.331101 # miss rate for demand accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.001859 # miss rate for demand accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_miss_rate::cpu1.data 0.040679 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total 0.173066 # miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.018812 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.data 0.331101 # miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.001859 # miss rate for overall accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_miss_rate::cpu1.data 0.040679 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total 0.173066 # miss rate for overall accesses
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 54670.857187 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 42360.847989 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54480.392157 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 64052.631579 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total 42963.106483 # average ReadReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 419.164702 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5761.903101 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 2439.894660 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 894.568690 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 192.796610 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 542.750929 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49348.616943 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64332.856713 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total 50163.648495 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 54670.857187 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 44445.702544 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 54480.392157 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 64322.812364 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total 45121.140186 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 54670.857187 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 44445.702544 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 54480.392157 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 64322.812364 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total 45121.140186 # average overall miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.writebacks::writebacks 78894 # number of writebacks
|
|
|
|
|
system.l2c.writebacks::total 78894 # number of writebacks
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits
|
|
|
|
|
system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
|
|
|
|
|
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
|
|
|
|
|
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 12926 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 271631 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 601 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 247 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::total 285405 # number of ReadReq MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2969 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1806 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_misses::total 4775 # number of UpgradeReq MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 939 # number of SCUpgradeReq MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 944 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1883 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 115505 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 6644 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses::total 122149 # number of ReadExReq MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_mshr_misses::cpu0.inst 12926 # number of demand (read+write) MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_mshr_misses::cpu0.data 387136 # number of demand (read+write) MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_mshr_misses::cpu1.inst 601 # number of demand (read+write) MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_mshr_misses::cpu1.data 6891 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::total 407554 # number of demand (read+write) MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_misses::cpu0.inst 12926 # number of overall MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_misses::cpu0.data 387136 # number of overall MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_misses::cpu1.inst 601 # number of overall MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_misses::cpu1.data 6891 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::total 407554 # number of overall MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 543164896 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7977851486 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 25213167 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12672975 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::total 8558902524 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29845964 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18081803 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 47927767 # number of UpgradeReq MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9405923 # number of SCUpgradeReq MSHR miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9440944 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 18846867 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207932893 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 343549452 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 4551482345 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 543164896 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 12185784379 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 25213167 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 356222427 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::total 13110384869 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 543164896 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 12185784379 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 25213167 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 356222427 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::total 13110384869 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373080000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18172000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 1391252000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2155311500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 683999000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 2839310500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3528391500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 702171000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency::total 4230562500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292124 # mshr miss rate for ReadReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002171 # mshr miss rate for ReadReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.138549 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944639 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.762025 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.866135 # mshr miss rate for UpgradeReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.963077 # mshr miss rate for SCUpgradeReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975207 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969120 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482493 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119462 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.414053 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for demand accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for demand accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total 0.173062 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for overall accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total 0.173062 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29370.180451 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 51307.591093 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 29988.621517 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.530818 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.072536 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.228691 # average UpgradeReq mshr miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.957401 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.957515 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36430.742332 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51708.225768 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 37261.724165 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-10-15 14:12:21 +02:00
|
|
|
system.iocache.replacements 41696 # number of replacements
|
2012-10-25 19:15:59 +02:00
|
|
|
system.iocache.tagsinuse 0.562950 # Cycle average of tags in use
|
2012-01-25 18:19:50 +01:00
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
2012-10-15 14:12:21 +02:00
|
|
|
system.iocache.sampled_refs 41712 # Sample count of references to valid blocks.
|
2012-01-25 18:19:50 +01:00
|
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit.
|
2012-10-25 19:15:59 +02:00
|
|
|
system.iocache.occ_blocks::tsunami.ide 0.562950 # Average occupied blocks per requestor
|
2012-10-25 19:14:42 +02:00
|
|
|
system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy
|
2012-10-15 14:12:21 +02:00
|
|
|
system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
|
|
|
|
|
system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
2012-10-15 14:12:21 +02:00
|
|
|
system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 41728 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 41728 # number of overall misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles
|
|
|
|
|
system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles
|
|
|
|
|
system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles
|
|
|
|
|
system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles
|
|
|
|
|
system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles
|
2012-10-15 14:12:21 +02:00
|
|
|
system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
2012-01-25 18:19:50 +01:00
|
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
2012-10-15 14:12:21 +02:00
|
|
|
system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency
|
|
|
|
|
system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency
|
|
|
|
|
system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-10-25 19:15:59 +02:00
|
|
|
system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-10-25 19:15:59 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2012-09-10 17:57:37 +02:00
|
|
|
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
|
|
|
|
system.iocache.writebacks::total 41520 # number of writebacks
|
2012-10-15 14:12:21 +02:00
|
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
|
|
|
|
|
system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
|
|
|
|
|
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
|
2012-10-15 14:12:21 +02:00
|
|
|
system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency
|
|
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency
|
|
|
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
|
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
|
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
|
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
|
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dtb.read_hits 7424685 # DTB read hits
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu0.dtb.read_misses 7443 # DTB read misses
|
|
|
|
|
system.cpu0.dtb.read_acv 210 # DTB read access violations
|
|
|
|
|
system.cpu0.dtb.read_accesses 490673 # DTB read accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dtb.write_hits 5011105 # DTB write hits
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu0.dtb.write_misses 813 # DTB write misses
|
|
|
|
|
system.cpu0.dtb.write_acv 134 # DTB write access violations
|
|
|
|
|
system.cpu0.dtb.write_accesses 187452 # DTB write accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dtb.data_hits 12435790 # DTB hits
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu0.dtb.data_misses 8256 # DTB misses
|
|
|
|
|
system.cpu0.dtb.data_acv 344 # DTB access violations
|
|
|
|
|
system.cpu0.dtb.data_accesses 678125 # DTB accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.itb.fetch_hits 3481701 # ITB hits
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu0.itb.fetch_misses 3871 # ITB misses
|
|
|
|
|
system.cpu0.itb.fetch_acv 184 # ITB acv
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.itb.fetch_accesses 3485572 # ITB accesses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.numCycles 3900399041 # number of cpu cycles simulated
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.committedInsts 47350784 # Number of instructions committed
|
|
|
|
|
system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses
|
|
|
|
|
system.cpu0.num_func_calls 1188579 # number of times a function call or return occured
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu0.num_int_insts 43919786 # number of integer instructions
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.num_fp_insts 206365 # number of float instructions
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read
|
|
|
|
|
system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read
|
|
|
|
|
system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.num_mem_refs 12475691 # number of memory refs
|
|
|
|
|
system.cpu0.num_load_insts 7451626 # Number of load instructions
|
|
|
|
|
system.cpu0.num_store_insts 5024065 # Number of store instructions
|
|
|
|
|
system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles
|
|
|
|
|
system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles
|
|
|
|
|
system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed
|
|
|
|
|
system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed
|
|
|
|
|
system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::total 222 # number of syscalls executed
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.kern.callpal::total 147588 # number of callpals executed
|
|
|
|
|
system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches
|
|
|
|
|
system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.kern.mode_good::kernel 1283
|
|
|
|
|
system.cpu0.kern.mode_good::user 1283
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.kern.mode_good::idle 0
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.kern.swap_context 3025 # number of times the context was actually changed
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
|
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
2012-01-25 18:19:50 +01:00
|
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
2012-01-25 18:19:50 +01:00
|
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
2012-01-25 18:19:50 +01:00
|
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
2012-01-25 18:19:50 +01:00
|
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
2006-07-27 23:47:43 +02:00
|
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
2012-01-25 18:19:50 +01:00
|
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
2012-01-25 18:19:50 +01:00
|
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
2012-01-25 18:19:50 +01:00
|
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
2012-01-25 18:19:50 +01:00
|
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
2012-05-09 20:52:14 +02:00
|
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
2012-01-25 18:19:50 +01:00
|
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
|
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.icache.replacements 686544 # number of replacements
|
|
|
|
|
system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit.
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 46672235 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.ReadReq_hits::total 46672235 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.demand_hits::cpu0.inst 46672235 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.demand_hits::total 46672235 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.overall_hits::cpu0.inst 46672235 # number of overall hits
|
|
|
|
|
system.cpu0.icache.overall_hits::total 46672235 # number of overall hits
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 687149 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::total 687149 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.demand_misses::cpu0.inst 687149 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.demand_misses::total 687149 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.overall_misses::cpu0.inst 687149 # number of overall misses
|
|
|
|
|
system.cpu0.icache.overall_misses::total 687149 # number of overall misses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9571696500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_latency::total 9571696500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 9571696500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.icache.demand_miss_latency::total 9571696500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 9571696500 # number of overall miss cycles
|
|
|
|
|
system.cpu0.icache.overall_miss_latency::total 9571696500 # number of overall miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359384 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses::total 47359384 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 47359384 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.demand_accesses::total 47359384 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 47359384 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_accesses::total 47359384 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014509 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.014509 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014509 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::total 0.014509 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014509 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::total 0.014509 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13929.579320 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13929.579320 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13929.579320 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13929.579320 # average overall miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687149 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 687149 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 687149 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.icache.demand_mshr_misses::total 687149 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 687149 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.icache.overall_mshr_misses::total 687149 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8197398500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 8197398500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8197398500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 8197398500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8197398500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 8197398500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014509 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.014509 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.014509 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11929.579320 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.replacements 1171731 # number of replacements
|
|
|
|
|
system.cpu0.dcache.tagsinuse 505.264467 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.dcache.total_refs 11253773 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.sampled_refs 1172148 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.avg_refs 9.600983 # Average number of references to valid blocks.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit.
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 505.264467 # Average occupied blocks per requestor
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6351999 # number of ReadReq hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_hits::total 6351999 # number of ReadReq hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 4607371 # number of WriteReq hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_hits::total 4607371 # number of WriteReq hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138396 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 138396 # number of LoadLockedReq hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.demand_hits::cpu0.data 10959370 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.dcache.demand_hits::total 10959370 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.dcache.overall_hits::cpu0.data 10959370 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.overall_hits::total 10959370 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 933038 # number of ReadReq misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_misses::total 933038 # number of ReadReq misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 249274 # number of WriteReq misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_misses::total 249274 # number of WriteReq misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13435 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 13435 # number of LoadLockedReq misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1182312 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.dcache.demand_misses::total 1182312 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1182312 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.overall_misses::total 1182312 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20824713000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 20824713000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7766651000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 7766651000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144248500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 144248500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43490500 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 43490500 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 28591364000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_miss_latency::total 28591364000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 28591364000 # number of overall miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_miss_latency::total 28591364000 # number of overall miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285037 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.ReadReq_accesses::total 7285037 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856645 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.WriteReq_accesses::total 4856645 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151831 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 151831 # number of LoadLockedReq accesses(hits+misses)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses)
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12141682 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.demand_accesses::total 12141682 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12141682 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_accesses::total 12141682 # number of overall (read+write) accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051326 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.051326 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088487 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088487 # miss rate for LoadLockedReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097376 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.demand_miss_rate::total 0.097376 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097376 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::total 0.097376 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22319.254950 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 22319.254950 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31157.084172 # average WriteReq miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 31157.084172 # average WriteReq miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10736.769632 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10736.769632 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7588.640726 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7588.640726 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 24182.588014 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 24182.588014 # average overall miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.writebacks::writebacks 672345 # number of writebacks
|
|
|
|
|
system.cpu0.dcache.writebacks::total 672345 # number of writebacks
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933038 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 933038 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249274 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 249274 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13435 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13435 # number of LoadLockedReq MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182312 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_misses::total 1182312 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182312 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dtb.read_hits 2500361 # DTB read hits
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu1.dtb.read_misses 2992 # DTB read misses
|
|
|
|
|
system.cpu1.dtb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu1.dtb.read_accesses 239363 # DTB read accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dtb.write_hits 1820984 # DTB write hits
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu1.dtb.write_misses 341 # DTB write misses
|
|
|
|
|
system.cpu1.dtb.write_acv 29 # DTB write access violations
|
|
|
|
|
system.cpu1.dtb.write_accesses 105247 # DTB write accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dtb.data_hits 4321345 # DTB hits
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu1.dtb.data_misses 3333 # DTB misses
|
|
|
|
|
system.cpu1.dtb.data_acv 29 # DTB access violations
|
|
|
|
|
system.cpu1.dtb.data_accesses 344610 # DTB accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.itb.fetch_hits 1990033 # ITB hits
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu1.itb.fetch_misses 1216 # ITB misses
|
|
|
|
|
system.cpu1.itb.fetch_acv 0 # ITB acv
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.itb.fetch_accesses 1991249 # ITB accesses
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.numCycles 3901627911 # number of cpu cycles simulated
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.committedInsts 13632233 # Number of instructions committed
|
|
|
|
|
system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.num_func_calls 426713 # number of times a function call or return occured
|
|
|
|
|
system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu1.num_int_insts 12571690 # number of integer instructions
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.num_fp_insts 180459 # number of float instructions
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read
|
|
|
|
|
system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read
|
|
|
|
|
system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.num_mem_refs 4345653 # number of memory refs
|
|
|
|
|
system.cpu1.num_load_insts 2515108 # Number of load instructions
|
|
|
|
|
system.cpu1.num_store_insts 1830545 # Number of store instructions
|
|
|
|
|
system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles
|
|
|
|
|
system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed
|
|
|
|
|
system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed
|
|
|
|
|
system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl
|
|
|
|
|
system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl
|
|
|
|
|
system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl
|
|
|
|
|
system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl
|
|
|
|
|
system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl
|
|
|
|
|
system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::total 104 # number of syscalls executed
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.kern.callpal::total 73828 # number of callpals executed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.kern.mode_switch::user 465 # number of protection mode switches
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.kern.mode_good::kernel 915
|
|
|
|
|
system.cpu1.kern.mode_good::user 465
|
|
|
|
|
system.cpu1.kern.mode_good::idle 450
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.kern.swap_context 2086 # number of times the context was actually changed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.icache.replacements 328646 # number of replacements
|
|
|
|
|
system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 13306402 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.ReadReq_hits::total 13306402 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.demand_hits::cpu1.inst 13306402 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.demand_hits::total 13306402 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.overall_hits::cpu1.inst 13306402 # number of overall hits
|
|
|
|
|
system.cpu1.icache.overall_hits::total 13306402 # number of overall hits
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 329194 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::total 329194 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.demand_misses::cpu1.inst 329194 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.demand_misses::total 329194 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.overall_misses::cpu1.inst 329194 # number of overall misses
|
|
|
|
|
system.cpu1.icache.overall_misses::total 329194 # number of overall misses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4346536000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_latency::total 4346536000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 4346536000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_latency::total 4346536000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 4346536000 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_latency::total 4346536000 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635596 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses::total 13635596 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 13635596 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.demand_accesses::total 13635596 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 13635596 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_accesses::total 13635596 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024142 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.024142 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024142 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::total 0.024142 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024142 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::total 0.024142 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13203.569931 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13203.569931 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13203.569931 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329194 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 329194 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 329194 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_misses::total 329194 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 329194 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_misses::total 329194 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688148000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688148000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688148000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 3688148000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688148000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 3688148000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024142 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.024142 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.024142 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11203.569931 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.replacements 172801 # number of replacements
|
|
|
|
|
system.cpu1.dcache.tagsinuse 487.450819 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.dcache.total_refs 4146327 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.sampled_refs 173313 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.avg_refs 23.923924 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.warmup_cycle 62292445000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 487.450819 # Average occupied blocks per requestor
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.952052 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.occ_percent::total 0.952052 # Average percentage of cache occupancy
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 2329216 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_hits::total 2329216 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 1699225 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits::total 1699225 # number of WriteReq hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50220 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52927 # number of StoreCondReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::total 52927 # number of StoreCondReq hits
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.demand_hits::cpu1.data 4028441 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.demand_hits::total 4028441 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.overall_hits::cpu1.data 4028441 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.overall_hits::total 4028441 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 123241 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::total 123241 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 64769 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::total 64769 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9346 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 9346 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6142 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::total 6142 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.demand_misses::cpu1.data 188010 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.demand_misses::total 188010 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.overall_misses::cpu1.data 188010 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.overall_misses::total 188010 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1494406500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 1494406500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166606000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 1166606000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85391000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 85391000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44592000 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 44592000 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 2661012500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_miss_latency::total 2661012500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 2661012500 # number of overall miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_miss_latency::total 2661012500 # number of overall miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452457 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::total 2452457 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763994 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::total 1763994 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59566 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 59566 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59069 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 59069 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 4216451 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.demand_accesses::total 4216451 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 4216451 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_accesses::total 4216451 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050252 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.050252 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036717 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.036717 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156902 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156902 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103980 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103980 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044590 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::total 0.044590 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044590 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::total 0.044590 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12125.887489 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12125.887489 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.795766 # average WriteReq miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.795766 # average WriteReq miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9136.635994 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9136.635994 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7260.175838 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7260.175838 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 14153.568959 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 14153.568959 # average overall miss latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.writebacks::writebacks 119125 # number of writebacks
|
|
|
|
|
system.cpu1.dcache.writebacks::total 119125 # number of writebacks
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123241 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 123241 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64769 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 64769 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9346 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9346 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6142 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 6142 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 188010 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_misses::total 188010 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 188010 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_misses::total 188010 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247924500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247924500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2012-01-25 18:19:50 +01:00
|
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-07-27 23:47:43 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
