2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-09-13 18:58:09 +02:00
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sim_seconds 0.483521 # Number of seconds simulated
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sim_ticks 483520764000 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-09-13 18:58:09 +02:00
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host_inst_rate 88254 # Simulator instruction rate (inst/s)
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host_tick_rate 24765480 # Simulator tick rate (ticks/s)
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host_mem_usage 263692 # Number of bytes of host memory used
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host_seconds 19523.98 # Real time elapsed on the host
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2011-08-19 22:08:08 +02:00
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sim_insts 1723073849 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 46 # Number of system calls
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2011-09-13 18:58:09 +02:00
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system.cpu.numCycles 967041529 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.lookups 298900449 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 243980938 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 18344304 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 264330532 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 238781777 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.usedRAS 17662867 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 3505 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 295983189 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2175588902 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 298900449 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 256444644 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 484812336 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 87085918 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 107601139 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 294 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 285066920 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 5311321 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 956724152 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.521766 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.026486 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::0 471911868 49.33% 49.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 35379148 3.70% 53.02% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 65139184 6.81% 59.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 66872594 6.99% 66.82% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 46913058 4.90% 71.73% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 59711536 6.24% 77.97% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 54259656 5.67% 83.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 17705492 1.85% 85.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 138831616 14.51% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::total 956724152 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.309088 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.249737 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 323003673 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 92138171 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 459624740 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 13631035 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 68326533 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 46888019 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 2352946295 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 2296 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 68326533 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 343140693 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 46558738 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 19729 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 451876616 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 46801843 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2296129706 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 19815 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 2700855 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 37763142 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 2264720698 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 10606897757 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 10606896049 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 1708 # Number of floating rename lookups
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2011-08-19 22:08:08 +02:00
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system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.UndoneMaps 558400742 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 819 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 812 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 98759000 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 618794544 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 222188124 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 74432694 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 62140550 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2187930244 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 806 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2018487398 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 3289652 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 458712680 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1051172668 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 349 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 956724152 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.109790 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.840040 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::0 261965292 27.38% 27.38% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 150944559 15.78% 43.16% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 168632678 17.63% 60.78% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 136410439 14.26% 75.04% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 125113434 13.08% 88.12% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 73446986 7.68% 95.80% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 29046356 3.04% 98.83% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 10235900 1.07% 99.90% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 928508 0.10% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::total 956724152 # Number of insts issued each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.fu_full::IntAlu 898312 3.71% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 170 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 18874903 77.94% 81.65% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 4444569 18.35% 100.00% # attempts to use FU when none available
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::IntAlu 1238989796 61.38% 61.38% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 1018767 0.05% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 11 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 1 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 583947158 28.93% 90.36% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 194531653 9.64% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 2018487398 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.087281 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 24217954 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.011998 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 5021206278 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 2646821889 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1958327848 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 276 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 2042705213 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 55649565 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 132867772 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 211365 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 180609 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 47341078 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 452178 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 68326533 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 22149991 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1213461 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2187949319 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 7278781 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 618794544 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 222188124 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 743 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 219838 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 61091 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 180609 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 18951981 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1826621 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 20778602 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1986068567 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 570288882 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 32418831 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_nop 18269 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 761473758 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 238644907 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 191184876 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.053757 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1967261719 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1958327963 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1288121662 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2036910460 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.wb_rate 2.025071 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.632390 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 464956551 # The number of squashed insts skipped by commit
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 457 # The number of times commit has been forced to stall to communicate backwards
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 18344332 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 888397620 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.939530 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.671610 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 383037346 43.12% 43.12% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 200906061 22.61% 65.73% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 81946763 9.22% 74.95% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 38644775 4.35% 79.30% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 19780530 2.23% 81.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 30949131 3.48% 85.01% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 22271905 2.51% 87.52% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 12048122 1.36% 88.88% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 98812987 11.12% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 888397620 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.count 1723073867 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.refs 660773817 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 485926771 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branches 213462365 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 98812987 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.rob.rob_reads 2977614452 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4444617859 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 920049 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 10317377 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.committedInsts 1723073849 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.cpi 0.561230 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.561230 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.781799 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.781799 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 9941893014 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1939859629 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 106 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 43 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 2914173755 # number of misc regfile reads
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.misc_regfile_writes 126 # number of misc regfile writes
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.replacements 10 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 611.960208 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 285065889 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 382125.856568 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 611.960208 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.298809 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 285065889 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 285065889 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 285065889 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 1031 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 1031 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 1031 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 35526500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 35526500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 35526500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 285066920 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 285066920 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 285066920 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 34458.292919 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 34458.292919 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 34458.292919 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 285 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 285 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 285 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 25635000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 25635000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 25635000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34363.270777 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 34363.270777 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 34363.270777 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.replacements 9570715 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4087.762174 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 666971462 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 9574811 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 69.658969 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 3484394000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4087.762174 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.997989 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 499575855 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 167395484 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 61 # number of LoadLockedReq hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_hits 666971339 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 666971339 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 10446749 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 5190563 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_misses 15637312 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 15637312 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 184495426500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 128540257604 # number of WriteReq miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 313035684104 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 313035684104 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 510022604 # number of ReadReq accesses(hits+misses)
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 64 # number of LoadLockedReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses 682608651 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 682608651 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.020483 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.030075 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.046875 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.022908 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.022908 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 17660.558945 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 24764.222610 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 20018.509837 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 20018.509837 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 267225153 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 199000 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 90802 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2942.943470 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 16583.333333 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.writebacks 3128462 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 2764582 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 3297919 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 6062501 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 6062501 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 7682167 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 1892644 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 9574811 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 9574811 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 92043723000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 45263737820 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 137307460820 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 137307460820 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015062 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.014027 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.014027 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.479054 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23915.611082 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 14340.487851 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 14340.487851 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.replacements 2927649 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 26780.067409 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 7851232 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2954973 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 2.656956 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 102089125500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 15983.054222 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 10797.013187 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.487764 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.329499 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 5655215 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 3128462 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 980262 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 6635477 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 6635477 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 2027697 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 912383 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 2940080 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 2940080 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 69611953000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 31645995500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 101257948500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 101257948500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 7682912 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 3128462 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1892645 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 9575557 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 9575557 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.263923 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.482068 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.307040 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.307040 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34330.549880 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.990295 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34440.541924 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34440.541924 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 56517000 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 6610 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8550.226929 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 1217515 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 2027686 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 912383 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 2940069 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 2940069 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 63233834500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28812323000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 92046157500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 92046157500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263922 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482068 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.307039 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.307039 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.220246 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31579.197552 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.482069 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.482069 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
