gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout

gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Jan 23 2012 03:53:29
gem5 started Jan 23 2012 04:23:09
gem5 executing on zizzer
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0.  Starting simulation...
info: Launching CPU 1 @ 562628000
Exiting @ tick 1958647095000 because m5_exit instruction encountered
stats: Update stats for final tick and memory bandwidth patches 2012-01-25 18:19:50 +01:00			`gem5 Simulator System. http://gem5.org`
			`gem5 is copyrighted software; use the --copyright option for details.`
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416 2006-07-27 23:47:43 +02:00
stats: Update stats for final tick and memory bandwidth patches 2012-01-25 18:19:50 +01:00			`gem5 compiled Jan 23 2012 03:53:29`
			`gem5 started Jan 23 2012 04:23:09`
			`gem5 executing on zizzer`
			`command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual`
update all the regresstion tests for release --HG-- extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2 2007-05-16 01:25:35 +02:00			`Global frequency set at 1000000000000 ticks per second`
stats: Update stats for final tick and memory bandwidth patches 2012-01-25 18:19:50 +01:00			`0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009`
Stats: Re update stats. 2011-02-08 04:23:13 +01:00			`info: kernel located at: /dist/m5/system/binaries/vmlinux`
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache. 2008-11-06 17:11:42 +01:00			`info: Entering event queue @ 0. Starting simulation...`
stats: update stats for previous cset Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes. 2010-09-22 08:07:35 +02:00			`info: Launching CPU 1 @ 562628000`
			`Exiting @ tick 1958647095000 because m5_exit instruction encountered`