2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2012-02-10 16:51:37 +01:00
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sim_seconds 0.104493 # Number of seconds simulated
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sim_ticks 104492506500 # Number of ticks simulated
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final_tick 104492506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-02-10 16:51:37 +01:00
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host_inst_rate 80425 # Simulator instruction rate (inst/s)
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host_tick_rate 24075162 # Simulator tick rate (ticks/s)
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host_mem_usage 264476 # Number of bytes of host memory used
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host_seconds 4340.26 # Real time elapsed on the host
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2011-12-01 09:15:23 +01:00
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sim_insts 349066034 # Number of instructions simulated
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2012-02-10 16:51:37 +01:00
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system.physmem.bytes_read 464000 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 192512 # Number of instructions bytes read from this memory
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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2012-02-10 16:51:37 +01:00
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system.physmem.num_reads 7250 # Number of read requests responded to by this memory
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2012-01-25 18:19:50 +01:00
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system.physmem.num_writes 0 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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2012-02-10 16:51:37 +01:00
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system.physmem.bw_read 4440510 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 1842352 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total 4440510 # Total bandwidth to/from this memory (bytes/s)
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 191 # Number of system calls
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2012-02-10 16:51:37 +01:00
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system.cpu.numCycles 208985014 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-02-10 16:51:37 +01:00
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system.cpu.BPredUnit.lookups 38314474 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 21092938 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3256966 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 27298627 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 21213565 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2012-02-10 16:51:37 +01:00
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system.cpu.BPredUnit.usedRAS 7683795 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 61136 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 43642080 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 338343690 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 38314474 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 28897360 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 78995706 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 10989579 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 78549841 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 41237520 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 904571 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 208872334 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.119807 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.192773 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2012-02-10 16:51:37 +01:00
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system.cpu.fetch.rateDist::0 130527843 62.49% 62.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 9429667 4.51% 67.01% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 6020154 2.88% 69.89% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 6750748 3.23% 73.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 5430125 2.60% 75.72% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 4858478 2.33% 78.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 3783272 1.81% 79.86% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 4242115 2.03% 81.89% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 37829932 18.11% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2012-02-10 16:51:37 +01:00
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system.cpu.fetch.rateDist::total 208872334 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.183336 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.618985 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 51215510 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 73658589 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 72565491 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 3819053 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 7613691 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 7463255 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 71181 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 431647720 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 198442 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 7613691 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 58863443 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 1188654 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 57607169 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 68932187 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 14667190 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 416637973 # Number of instructions processed by rename
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2011-12-01 09:15:23 +01:00
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system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full
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2012-02-10 16:51:37 +01:00
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system.cpu.rename.LSQFullEvents 8032684 # Number of times rename has blocked due to LSQ full
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers
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2012-02-10 16:51:37 +01:00
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system.cpu.rename.RenamedOperands 455385433 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 2446563589 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 1351891912 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 1094671677 # Number of floating rename lookups
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2011-12-01 09:15:23 +01:00
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system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed
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2012-02-10 16:51:37 +01:00
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system.cpu.rename.UndoneMaps 70816834 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 3986585 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 4043449 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 48232782 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 108804127 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 93109820 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 3374999 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 2307513 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 394258042 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 3864226 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 379117437 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1806866 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 46393196 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 143558304 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 308585 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 208872334 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.815068 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.996247 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2012-02-10 16:51:37 +01:00
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system.cpu.iq.issued_per_cycle::0 82047947 39.28% 39.28% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 34785806 16.65% 55.94% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 24508634 11.73% 67.67% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 18508923 8.86% 76.53% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 21724585 10.40% 86.93% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 15318663 7.33% 94.27% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 8418302 4.03% 98.30% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 2689665 1.29% 99.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 869809 0.42% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2012-02-10 16:51:37 +01:00
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system.cpu.iq.issued_per_cycle::total 208872334 # Number of insts issued each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2012-02-10 16:51:37 +01:00
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system.cpu.iq.fu_full::IntAlu 2261 0.01% 0.01% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
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2012-02-10 16:51:37 +01:00
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system.cpu.iq.fu_full::SimdFloatAdd 10246 0.06% 0.10% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
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2012-02-10 16:51:37 +01:00
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system.cpu.iq.fu_full::SimdFloatCmp 2469 0.01% 0.12% # attempts to use FU when none available
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2011-12-01 09:15:23 +01:00
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system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available
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2012-02-10 16:51:37 +01:00
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|
|
system.cpu.iq.fu_full::SimdFloatMisc 64552 0.37% 0.49% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 790 0.00% 0.49% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 177361 1.02% 1.52% # attempts to use FU when none available
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iq.fu_full::MemRead 9662090 55.64% 57.16% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 7440153 42.84% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 129612173 34.19% 34.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 2147283 0.57% 34.75% # Type of FU issued
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 15 0.00% 34.75% # Type of FU issued
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 6745842 1.78% 36.53% # Type of FU issued
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 8678031 2.29% 38.82% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 3497767 0.92% 39.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1584514 0.42% 40.16% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 21146877 5.58% 45.74% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 7187357 1.90% 47.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7146686 1.89% 49.52% # Type of FU issued
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 103748568 27.37% 76.93% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 87447038 23.07% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 379117437 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.814089 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 17365346 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.045805 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 735356252 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 310675933 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 251537712 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 250923168 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 133847541 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 118277096 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 267613476 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 128869307 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 7295740 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 14155127 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 112471 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 8340 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 10733989 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 274 # Number of loads that were rescheduled
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 7613691 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 19337 # Number of cycles IEW is blocking
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iew.iewDispatchedInsts 398169516 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2638152 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 108804127 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 93109820 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 3853005 # Number of dispatched non-speculative instructions
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iew.memOrderViolationEvents 8340 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 3192687 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 308539 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 3501226 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 373035381 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 102118243 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 6082056 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iew.exec_nop 47248 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 188073317 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 32214551 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 85955074 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.784986 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 370819014 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 369814808 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 175635069 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 345639533 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.iew.wb_rate 1.769576 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.508145 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 349066646 # The number of committed instructions
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 49103053 # The number of squashed insts skipped by commit
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.commit.branchMispredicts 3227876 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 201258644 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.734418 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.321139 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 89876372 44.66% 44.66% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 39560210 19.66% 64.31% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 17969648 8.93% 73.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 13168483 6.54% 79.79% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 14551255 7.23% 87.02% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 7589820 3.77% 90.79% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 3505620 1.74% 92.53% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 3424037 1.70% 94.23% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 11613199 5.77% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 201258644 # Number of insts commited each cycle
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.count 349066646 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.refs 177024831 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 94649000 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 11033 # Number of memory barriers committed
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.branches 30521879 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.commit.int_insts 279585929 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.commit.bw_lim_events 11613199 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.rob.rob_reads 587812621 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 803956224 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 112680 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.committedInsts 349066034 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 349066034 # Number of Instructions Simulated
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.cpi 0.598698 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.598698 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.670292 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.670292 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 1781918480 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 235832393 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 188783884 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 133870920 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 1003409978 # number of misc regfile reads
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.icache.replacements 14108 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1842.733120 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 41220872 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 15988 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 2578.238179 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.icache.occ_blocks::0 1842.733120 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.899772 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 41220872 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 41220872 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 41220872 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 16648 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 16648 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 16648 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 201025000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 201025000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 201025000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 41237520 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 41237520 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 41237520 # number of overall (read+write) accesses
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000404 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000404 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000404 # miss rate for overall accesses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 12075.024027 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 12075.024027 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 12075.024027 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 637 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 637 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 637 # number of overall MSHR hits
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 16011 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 16011 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 16011 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 135953500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 135953500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 135953500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8491.256011 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 8491.256011 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 8491.256011 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.replacements 1410 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 3098.497902 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 176602100 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 4594 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 38441.902481 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.occ_blocks::0 3098.497902 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.756469 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 94546395 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 82033205 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 11358 # number of LoadLockedReq hits
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_hits 11114 # number of StoreCondReq hits
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.demand_hits 176579600 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 176579600 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 3383 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.demand_misses 22872 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 22872 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 111712500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 649715000 # number of WriteReq miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.demand_miss_latency 761427500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 761427500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 94549778 # number of ReadReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses)
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 11360 # number of LoadLockedReq accesses(hits+misses)
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_accesses 11114 # number of StoreCondReq accesses(hits+misses)
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.demand_accesses 176602472 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 176602472 # number of overall (read+write) accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000238 # miss rate for WriteReq accesses
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.demand_miss_rate 0.000130 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000130 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 33021.726278 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 33337.523731 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 33290.814096 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 33290.814096 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.writebacks 1034 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 1633 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 16622 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.demand_mshr_hits 18255 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 18255 # number of overall MSHR hits
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 1750 # number of ReadReq MSHR misses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 2867 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 4617 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 4617 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 53344000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 101787500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 155131500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 155131500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30482.285714 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35503.139170 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 33600.064977 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 33600.064977 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.l2cache.replacements 57 # number of replacements
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 3892.486015 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 13341 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 5352 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 2.492713 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::0 3513.908293 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 378.577721 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.107236 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.011553 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 13258 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 1034 # number of Writeback hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 19 # number of ReadExReq hits
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.l2cache.demand_hits 13277 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 13277 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 4479 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 23 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 2826 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 7305 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 7305 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 153679500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 97429500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 251109000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 251109000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 17737 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 1034 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 23 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 2845 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 20582 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 20582 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.252523 # miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.993322 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.354922 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.354922 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34311.118553 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34476.114650 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34374.948665 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34374.948665 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4424 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 23 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 2826 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 7250 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 7250 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 137822500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 713000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88418000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 226240500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 226240500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249422 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993322 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.352250 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.352250 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.367993 # average ReadReq mshr miss latency
|
2011-12-01 09:15:23 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2012-02-10 16:51:37 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31287.331918 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.586207 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.586207 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
