2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:08 +02:00
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sim_seconds 0.105165 # Number of seconds simulated
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sim_ticks 105165052500 # Number of ticks simulated
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:08 +02:00
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host_inst_rate 98655 # Simulator instruction rate (inst/s)
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host_tick_rate 29722313 # Simulator tick rate (ticks/s)
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host_mem_usage 272452 # Number of bytes of host memory used
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host_seconds 3538.25 # Real time elapsed on the host
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sim_insts 349066014 # Number of instructions simulated
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2011-01-18 23:30:06 +01:00
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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2011-05-23 17:59:13 +02:00
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 191 # Number of system calls
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2011-08-19 22:08:08 +02:00
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system.cpu.numCycles 210330106 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.lookups 38627930 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 21275864 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3257223 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 27645633 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 21400607 # Number of BTB hits
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.usedRAS 7694267 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 65033 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 44094135 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 341080803 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 38627930 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 29094874 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 79585948 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 11338001 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 78589152 # Number of cycles fetch has spent blocked
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.CacheLines 41622030 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 918575 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 210218055 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.123854 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.194738 # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::0 131312097 62.46% 62.46% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 9414467 4.48% 66.94% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 6051481 2.88% 69.82% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 6791526 3.23% 73.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 5430399 2.58% 75.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 4963864 2.36% 78.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 3858971 1.84% 79.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 4276288 2.03% 81.87% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 38118962 18.13% 100.00% # Number of instructions fetched each cycle (Total)
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2011-01-18 23:30:06 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::total 210218055 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.183654 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.621645 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 51714033 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 73744287 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 72994348 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 3887626 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 7877761 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 7589058 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 71126 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 434888611 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 197240 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 7877761 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 59389931 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 1170243 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 57751426 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 69399524 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 14629170 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 419355645 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 21743 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 8031956 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 92 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 459021692 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 2465031741 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 1360499222 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 1104532519 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 384568567 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 74453120 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 3990661 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 4048076 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 47737584 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 109099510 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 93607240 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 6092384 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 2874940 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 396088689 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 3868258 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 378790544 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 2203147 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 48219539 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 157035108 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 312812 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 210218055 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.801893 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.982792 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::0 82551519 39.27% 39.27% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 35288638 16.79% 56.06% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 24974853 11.88% 67.94% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 18906763 8.99% 76.93% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 21633905 10.29% 87.22% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 15100886 7.18% 94.41% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 8378665 3.99% 98.39% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 2542737 1.21% 99.60% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 840089 0.40% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::total 210218055 # Number of insts issued each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.fu_full::IntAlu 2335 0.01% 0.01% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 47491 0.28% 0.32% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.32% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 2600 0.02% 0.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 370 0.00% 0.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 62973 0.37% 0.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 771 0.00% 0.71% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 174751 1.02% 1.73% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.73% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 9256583 54.09% 55.82% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 7559769 44.18% 100.00% # attempts to use FU when none available
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::IntAlu 129785467 34.26% 34.26% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 2147242 0.57% 34.83% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.83% # Type of FU issued
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|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 19 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.83% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 6801299 1.80% 36.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.63% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 8678326 2.29% 38.92% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 3497449 0.92% 39.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1584673 0.42% 40.26% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 21181771 5.59% 45.85% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 7250646 1.91% 47.76% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7280640 1.92% 49.69% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 103263582 27.26% 76.99% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 87144142 23.01% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 378790544 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.800934 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 17112689 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.045177 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 735684674 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 312839753 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 251076312 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 251430305 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 135519502 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 118553768 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 266787824 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 129115409 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 5590978 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 14450513 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 33283 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 183129 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 11231413 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 279 # Number of loads that were rescheduled
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 7877761 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 19485 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 447 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 400004247 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2635197 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 109099510 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 93607240 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 3857036 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 197 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 183129 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 3190070 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 310107 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 3500177 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 372762431 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 101699346 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 6028113 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.exec_nop 47300 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 187402554 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 32194166 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 85703208 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.772273 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 370566710 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 369630080 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 175670846 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 345667025 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.wb_rate 1.757381 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.508208 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 349066626 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 50932905 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 3555446 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 3228207 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 202340295 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.725146 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.308674 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 90698081 44.82% 44.82% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 39477240 19.51% 64.33% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 17960460 8.88% 73.21% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 13374711 6.61% 79.82% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 15019988 7.42% 87.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 7480519 3.70% 90.94% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 3574486 1.77% 92.71% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 3423610 1.69% 94.40% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 11331200 5.60% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 202340295 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 349066626 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.refs 177024823 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 94648996 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 11033 # Number of memory barriers committed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branches 30521875 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.int_insts 279585913 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.bw_lim_events 11331200 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.rob.rob_reads 591006103 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 807880090 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 112051 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 349066014 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 349066014 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.602551 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.602551 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.659610 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.659610 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 1778945060 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 235524211 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 190068131 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 134456133 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 1007398689 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 34422185 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 14113 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1843.325990 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 41605379 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 15990 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 2601.962414 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1843.325990 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.900062 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 41605379 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 41605379 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 41605379 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 16651 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 16651 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 16651 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 201600500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 201600500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 201600500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 41622030 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 41622030 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 41622030 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000400 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000400 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000400 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 12107.410966 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 12107.410966 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 12107.410966 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 658 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 658 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 658 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 15993 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 15993 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 15993 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 136019500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 136019500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 136019500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000384 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000384 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000384 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8504.939661 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 8504.939661 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 8504.939661 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.replacements 1412 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 3102.801650 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 177884115 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 4603 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 38645.256355 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 3102.801650 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.757520 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 95828379 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 82033251 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 11362 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits 11110 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 177861630 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 177861630 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 3434 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 19443 # number of WriteReq misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_misses 22877 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 22877 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 113492500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 646306000 # number of WriteReq miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 759798500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 759798500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 95831813 # number of ReadReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 11364 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses 11110 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 177884507 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 177884507 # number of overall (read+write) accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 33049.650553 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 33241.063622 # average WriteReq miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency 33212.331162 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 33212.331162 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 307000 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.writebacks 1031 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 1669 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 16602 # number of WriteReq MSHR hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 18271 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 18271 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 1765 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 2841 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 4606 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 4606 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 53909000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 100913500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 154822500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 154822500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30543.342776 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35520.415347 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 33613.221884 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 33613.221884 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.replacements 60 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 3910.737339 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 13339 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 5367 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 2.485374 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 3534.138059 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 376.599280 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.107853 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.011493 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 13255 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 1031 # number of Writeback hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 18 # number of ReadExReq hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.demand_hits 13273 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 13273 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 4498 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 2821 # number of ReadExReq misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.demand_misses 7319 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 7319 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 154344500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 97273500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 251618000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 251618000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 17753 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 1031 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses)
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 2839 # number of ReadExReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 20592 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 20592 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.253366 # miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.993660 # miss rate for ReadExReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.355429 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.355429 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34314.028457 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34481.921305 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34378.740265 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34378.740265 # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4443 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 2821 # number of ReadExReq MSHR misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 7264 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 7264 # number of overall MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 138429500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88249000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 226678500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 226678500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250268 # mshr miss rate for ReadReq accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993660 # mshr miss rate for ReadExReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.352758 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.352758 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.763448 # average ReadReq mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31282.878412 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.740639 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.740639 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
