gem5/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000020                       # Number of seconds simulated
sim_ticks                                    19785000                       # Number of ticks simulated
final_tick                                   19785000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  71616                       # Simulator instruction rate (inst/s)
host_tick_rate                              243111037                       # Simulator tick rate (ticks/s)
host_mem_usage                                 208328                       # Number of bytes of host memory used
host_seconds                                     0.08                       # Real time elapsed on the host
sim_insts                                        5827                       # Number of instructions simulated
system.physmem.bytes_read                       29120                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                  20288                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                        0                       # Number of bytes written to this memory
system.physmem.num_reads                          455                       # Number of read requests responded to by this memory
system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                     1471822087                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                1025423300                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total                    1471822087                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                    8                       # Number of system calls
system.cpu.numCycles                            39571                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.threadCycles                          9159                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                             403                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           34166                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                             5405                       # Number of cycles cpu stages are processed.
system.cpu.activity                         13.658993                       # Percentage of cycles cpu is active
system.cpu.comLoads                              1164                       # Number of Load instructions committed
system.cpu.comStores                              925                       # Number of Store instructions committed
system.cpu.comBranches                            916                       # Number of Branches instructions committed
system.cpu.comNops                                657                       # Number of Nop instructions committed
system.cpu.comNonSpec                              10                       # Number of Non-Speculative instructions committed
system.cpu.comInts                               2155                       # Number of Integer instructions committed
system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
system.cpu.committedInsts                        5827                       # Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total                  5827                       # Number of Instructions Simulated (Total)
system.cpu.cpi                               6.790973                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
system.cpu.cpi_total                         6.790973                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.147254                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         0.147254                       # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups              1185                       # Number of BP lookups
system.cpu.branch_predictor.condPredicted          896                       # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect          611                       # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups           1035                       # Number of BTB lookups
system.cpu.branch_predictor.BTBHits               443                       # Number of BTB hits
system.cpu.branch_predictor.usedRAS                86                       # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect           32                       # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct       42.801932                       # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken          536                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken          649                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads         5108                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites         3408                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses         8516                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads            3                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites            1                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses            4                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards           1344                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                       2228                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect          317                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect          285                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted            602                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted               314                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     65.720524                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions             3132                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
system.cpu.stage0.idleCycles                    35846                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                      3725                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization                9.413459                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles                    36723                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                      2848                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization                7.197190                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles                    36778                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                      2793                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization                7.058199                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles                    38328                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                      1243                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization                3.141189                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                    36666                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                      2905                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization                7.341235                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements                     13                       # number of replacements
system.cpu.icache.tagsinuse                148.138598                       # Cycle average of tags in use
system.cpu.icache.total_refs                      443                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    319                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   1.388715                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0            148.138598                       # Average occupied blocks per context
system.cpu.icache.occ_percent::0             0.072333                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits                    443                       # number of ReadReq hits
system.cpu.icache.demand_hits                     443                       # number of demand (read+write) hits
system.cpu.icache.overall_hits                    443                       # number of overall hits
system.cpu.icache.ReadReq_misses                  341                       # number of ReadReq misses
system.cpu.icache.demand_misses                   341                       # number of demand (read+write) misses
system.cpu.icache.overall_misses                  341                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency       19027500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency        19027500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency       19027500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses                784                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses                 784                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses                784                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate          0.434949                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate           0.434949                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate          0.434949                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 55799.120235                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 55799.120235                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 55799.120235                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets        29000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits                22                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits                 22                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits                22                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses             319                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses              319                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses             319                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency     16952500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency     16952500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency     16952500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.406888                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate      0.406888                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate     0.406888                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.tagsinuse                 89.732679                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     1838                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  13.318841                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0             89.732679                       # Average occupied blocks per context
system.cpu.dcache.occ_percent::0             0.021907                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits                   1075                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits                   763                       # number of WriteReq hits
system.cpu.dcache.demand_hits                    1838                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits                   1838                       # number of overall hits
system.cpu.dcache.ReadReq_misses                   89                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses                 162                       # number of WriteReq misses
system.cpu.dcache.demand_misses                   251                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses                  251                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency        5072500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency       8912000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency        13984500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency       13984500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses               1164                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses               925                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses                2089                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses               2089                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate          0.076460                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate         0.175135                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate           0.120153                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate          0.120153                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 55715.139442                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 55715.139442                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      1153500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              23                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits                 2                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits              111                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits                113                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits               113                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses              87                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses             51                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses              138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses             138                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency      4702500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency      2746000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency      7448500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency      7448500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.074742                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate     0.055135                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate      0.066060                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate     0.066060                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53843.137255                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53974.637681                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53974.637681                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse               205.469583                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                   404                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.004950                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0           205.469583                       # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0            0.006270                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits                     2                       # number of overall hits
system.cpu.l2cache.ReadReq_misses                 404                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses                51                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses                  455                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses                 455                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency      21170500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency      2682500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency       23853000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency      23853000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses               406                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses              51                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses                457                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses               457                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate         0.995074                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate          0.995624                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate         0.995624                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52424.175824                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52424.175824                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses            404                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses           51                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses             455                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses            455                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency     16247000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency      2058000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency     18305000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency     18305000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.995074                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate     0.995624                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate     0.995624                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40215.346535                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40352.941176                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40230.769231                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40230.769231                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------