2009-05-13 07:55:04 +02:00
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---------- Begin Simulation Statistics ----------
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2011-06-20 03:43:42 +02:00
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sim_seconds 0.000020 # Number of seconds simulated
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sim_ticks 19782000 # Number of ticks simulated
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2009-05-13 07:55:04 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-06-20 03:43:42 +02:00
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host_inst_rate 56447 # Simulator instruction rate (inst/s)
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host_tick_rate 191567423 # Simulator tick rate (ticks/s)
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host_mem_usage 158160 # Number of bytes of host memory used
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host_seconds 0.10 # Real time elapsed on the host
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2009-12-31 21:30:51 +01:00
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sim_insts 5827 # Number of instructions simulated
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2011-06-20 03:43:42 +02:00
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 8 # Number of system calls
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system.cpu.numCycles 39565 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 9153 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 34165 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 5400 # Number of cycles cpu stages are processed.
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system.cpu.activity 13.648427 # Percentage of cycles cpu is active
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2010-06-24 00:21:44 +02:00
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system.cpu.comLoads 1164 # Number of Load instructions committed
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system.cpu.comStores 925 # Number of Store instructions committed
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2011-06-20 03:43:42 +02:00
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system.cpu.comBranches 916 # Number of Branches instructions committed
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system.cpu.comNops 657 # Number of Nop instructions committed
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system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed
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system.cpu.comInts 2155 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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2009-12-31 21:30:51 +01:00
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system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread)
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2011-06-20 03:43:42 +02:00
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
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2009-12-31 21:30:51 +01:00
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system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total)
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2011-06-20 03:43:42 +02:00
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system.cpu.cpi 6.789943 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
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system.cpu.cpi_total 6.789943 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.147277 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.147277 # IPC: Total IPC of All Threads
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system.cpu.branch_predictor.lookups 1173 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 886 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 609 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 1011 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 413 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 40.850643 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 506 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 667 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5107 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 8515 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 1342 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 2229 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 313 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 287 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 600 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 316 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 65.502183 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 3130 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
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system.cpu.stage0.idleCycles 35845 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 3720 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 9.402249 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 36724 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 2841 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 7.180589 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 36774 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 7.054215 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 38322 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 3.141666 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 36660 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 7.342348 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 13 # number of replacements
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system.cpu.icache.tagsinuse 148.154290 # Cycle average of tags in use
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system.cpu.icache.total_refs 442 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1.385580 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 148.154290 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.072341 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits 442 # number of ReadReq hits
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system.cpu.icache.demand_hits 442 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 442 # number of overall hits
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system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses
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system.cpu.icache.demand_misses 341 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 341 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency 19026500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 19026500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 19026500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 783 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 783 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 783 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.435504 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.435504 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.435504 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 55796.187683 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 55796.187683 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 55796.187683 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.ReadReq_mshr_miss_latency 16952000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 16952000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 16952000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.407407 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate 0.407407 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate 0.407407 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53141.065831 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 53141.065831 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 53141.065831 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 89.737794 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::0 89.737794 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.021909 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits
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system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits 1838 # number of overall hits
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system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses 162 # number of WriteReq misses
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system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses 251 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency 8910500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency 13983000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency 13983000 # number of overall miss cycles
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2010-02-01 00:31:28 +01:00
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system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
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2009-12-31 21:30:51 +01:00
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system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
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2011-06-20 03:43:42 +02:00
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system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate 0.076460 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate 0.175135 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 55003.086420 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency 55709.163347 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 55709.163347 # average overall miss latency
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2009-05-13 07:55:04 +02:00
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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2011-06-20 03:43:42 +02:00
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system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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2009-05-13 07:55:04 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-06-20 03:43:42 +02:00
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits 111 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits 113 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits 113 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
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2009-05-13 07:55:04 +02:00
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2745500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 7448000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 7448000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53833.333333 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 53971.014493 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 53971.014493 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 205.489748 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 205.489748 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.006271 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses
|
2009-12-31 21:30:51 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 455 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 21170000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2682000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 23852000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 23852000 # number of overall miss cycles
|
2011-02-04 06:09:22 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses)
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses
|
2011-02-04 06:09:22 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52400.990099 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52588.235294 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 52421.978022 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 52421.978022 # average overall miss latency
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses
|
2011-02-04 06:09:22 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 16247000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2058000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 18305000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 18305000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40215.346535 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40352.941176 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2009-05-13 07:55:04 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2009-05-13 07:55:04 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
