gem5/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt

---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits                     37055347                       # Number of BTB hits
global.BPredUnit.BTBLookups                  45947414                       # Number of BTB lookups
global.BPredUnit.RASInCorrect                    1096                       # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect                5691744                       # Number of conditional branches incorrect
global.BPredUnit.condPredicted               35558640                       # Number of conditional branches predicted
global.BPredUnit.lookups                     62480259                       # Number of BP lookups
global.BPredUnit.usedRAS                     12398507                       # Number of times the RAS was used to get a target.
host_inst_rate                                  99164                       # Simulator instruction rate (inst/s)
host_mem_usage                                 157680                       # Number of bytes of host memory used
host_seconds                                  3787.43                       # Real time elapsed on the host
host_tick_rate                               35615266                       # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads           72769124                       # Number of conflicting loads.
memdepunit.memDep.conflictingStores          54049353                       # Number of conflicting stores.
memdepunit.memDep.insertedLoads             125306666                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores             92782205                       # Number of stores inserted to the mem dependence unit.
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   375574819                       # Number of instructions simulated
sim_seconds                                  0.134890                       # Number of seconds simulated
sim_ticks                                134890208500                       # Number of ticks simulated
system.cpu.commit.COM:branches               44587532                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events          13065530                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples    254286247                      
system.cpu.commit.COM:committed_per_cycle.min_value            0                      
                               0    123470433   4855.57%           
                               1     49744073   1956.22%           
                               2     18820215    740.12%           
                               3     19293865    758.75%           
                               4     12510791    492.00%           
                               5      8575068    337.22%           
                               6      5688152    223.69%           
                               7      3118120    122.62%           
                               8     13065530    513.81%           
system.cpu.commit.COM:committed_per_cycle.max_value            8                      
system.cpu.commit.COM:committed_per_cycle.end_dist

system.cpu.commit.COM:count                 398664594                       # Number of instructions committed
system.cpu.commit.COM:loads                 100651995                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                  174183397                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts           5687554                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts      398664594                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts        96777858                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                   375574819                       # Number of Instructions Simulated
system.cpu.committedInsts_total             375574819                       # Number of Instructions Simulated
system.cpu.cpi                               0.718313                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.718313                       # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses            1                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits                1                       # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses           95885716                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency  9843.626807                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7312.880325                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits               95884194                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency       14982000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                 1522                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits               536                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency      7210500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses             986                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses          73520729                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency  9673.649142                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7598.791541                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              73509773                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency     105984500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.000149                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses               10956                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits             7646                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency     25152000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.000045                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses           3310                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs               40554.032799                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           169406445                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency  9694.382113                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency  7533.170391                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               169393967                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency       120966500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.000074                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                 12478                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits               8182                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency     32362500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses             4296                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses          169406445                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency  9694.382113                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency  7533.170391                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              169393967                       # number of overall hits
system.cpu.dcache.overall_miss_latency      120966500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.000074                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                12478                       # number of overall misses
system.cpu.dcache.overall_mshr_hits              8182                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency     32362500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses            4296                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements                    781                       # number of replacements
system.cpu.dcache.sampled_refs                   4177                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               3296.858616                       # Cycle average of tags in use
system.cpu.dcache.total_refs                169394195                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                      636                       # number of writebacks
system.cpu.decode.DECODE:BlockedCycles       18955564                       # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred           4312                       # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved      11369096                       # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts       533723337                       # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles         133094788                       # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles          100949486                       # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles        15490881                       # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts          12729                       # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles        1286410                       # Number of cycles decode is unblocking
system.cpu.dtb.accesses                     186077432                       # DTB accesses
system.cpu.dtb.acv                              11216                       # DTB access violations
system.cpu.dtb.hits                         186006805                       # DTB hits
system.cpu.dtb.misses                           70627                       # DTB misses
system.cpu.dtb.read_accesses                104841123                       # DTB read accesses
system.cpu.dtb.read_acv                         11216                       # DTB read access violations
system.cpu.dtb.read_hits                    104772046                       # DTB read hits
system.cpu.dtb.read_misses                      69077                       # DTB read misses
system.cpu.dtb.write_accesses                81236309                       # DTB write accesses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_hits                    81234759                       # DTB write hits
system.cpu.dtb.write_misses                      1550                       # DTB write misses
system.cpu.fetch.Branches                    62480259                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                  64020665                       # Number of cache lines fetched
system.cpu.fetch.Cycles                     168778939                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes               1468351                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                      547045642                       # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles                 6042059                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.231597                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles           64020665                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches           49453854                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        2.027744                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples           269777129                      
system.cpu.fetch.rateDist.min_value                 0                      
                               0    165019149   6116.87%           
                               1     11208105    415.46%           
                               2     10970042    406.63%           
                               3      7809028    289.46%           
                               4     16007682    593.37%           
                               5      8770390    325.10%           
                               6      6686429    247.85%           
                               7      3981315    147.58%           
                               8     39324989   1457.68%           
system.cpu.fetch.rateDist.max_value                 8                      
system.cpu.fetch.rateDist.end_dist

system.cpu.icache.ReadReq_accesses           64020665                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency  8765.688380                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency  6021.951220                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits               64016474                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       36737000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000065                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                 4191                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits               296                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency     23455500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000061                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses            3895                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               16435.551733                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses            64020665                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency  8765.688380                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency  6021.951220                       # average overall mshr miss latency
system.cpu.icache.demand_hits                64016474                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        36737000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000065                       # miss rate for demand accesses
system.cpu.icache.demand_misses                  4191                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                296                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     23455500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000061                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses             3895                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses           64020665                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency  8765.688380                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency  6021.951220                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits               64016474                       # number of overall hits
system.cpu.icache.overall_miss_latency       36737000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000065                       # miss rate for overall accesses
system.cpu.icache.overall_misses                 4191                       # number of overall misses
system.cpu.icache.overall_mshr_hits               296                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     23455500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000061                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses            3895                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements                   1973                       # number of replacements
system.cpu.icache.sampled_refs                   3895                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1826.958701                       # Cycle average of tags in use
system.cpu.icache.total_refs                 64016474                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                            3290                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches                 51062363                       # Number of branches executed
system.cpu.iew.EXEC:nop                      27214999                       # number of nop insts executed
system.cpu.iew.EXEC:rate                     1.560789                       # Inst execution rate
system.cpu.iew.EXEC:refs                    192842691                       # number of memory reference insts executed
system.cpu.iew.EXEC:stores                   81246989                       # Number of stores executed
system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
system.cpu.iew.WB:consumers                 287107823                       # num instructions consuming a value
system.cpu.iew.WB:count                     417299912                       # cumulative count of insts written-back
system.cpu.iew.WB:fanout                     0.702706                       # average fanout of values written-back
system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers                 201752289                       # num instructions producing a value
system.cpu.iew.WB:rate                       1.546813                       # insts written-back per cycle
system.cpu.iew.WB:sent                      418066212                       # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts              6311133                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles                 2198946                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts             125306666                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts                239                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts           6339692                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts             92782205                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts           495443138                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts             111595702                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10411801                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts             421070304                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                 127438                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                 23538                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles               15490881                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                491568                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads         8710387                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses         3327                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation       505299                       # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads       175942                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads     24654671                       # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores     19250803                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents         505299                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect       821714                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect        5489419                       # Number of branches that were predicted taken incorrectly
system.cpu.ipc                               1.392150                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.392150                       # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0               431482105                       # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
                      No_OpClass        33581      0.01%            # Type of FU issued
                          IntAlu    167002612     38.70%            # Type of FU issued
                         IntMult      2153139      0.50%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd     34874757      8.08%            # Type of FU issued
                        FloatCmp      7889981      1.83%            # Type of FU issued
                        FloatCvt      2903377      0.67%            # Type of FU issued
                       FloatMult     16803027      3.89%            # Type of FU issued
                        FloatDiv      1591666      0.37%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead    114230521     26.47%            # Type of FU issued
                        MemWrite     83999444     19.47%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt              10446664                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate             0.024211                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
                      No_OpClass            0      0.00%            # attempts to use FU when none available
                          IntAlu        32363      0.31%            # attempts to use FU when none available
                         IntMult            0      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd        95689      0.92%            # attempts to use FU when none available
                        FloatCmp         7492      0.07%            # attempts to use FU when none available
                        FloatCvt        12721      0.12%            # attempts to use FU when none available
                       FloatMult      1683122     16.11%            # attempts to use FU when none available
                        FloatDiv      1408746     13.49%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead      5941492     56.87%            # attempts to use FU when none available
                        MemWrite      1265039     12.11%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples    269777129                      
system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
                               0     99508340   3688.54%           
                               1     57898126   2146.15%           
                               2     39403533   1460.60%           
                               3     28850583   1069.42%           
                               4     24598298    911.80%           
                               5     10625217    393.85%           
                               6      6146486    227.84%           
                               7      2145397     79.52%           
                               8       601149     22.28%           
system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
system.cpu.iq.ISSUE:issued_per_cycle.end_dist

system.cpu.iq.ISSUE:rate                     1.599383                       # Inst issue rate
system.cpu.iq.iqInstsAdded                  468227900                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                 431482105                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                 239                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined        91553989                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued           1306748                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved             24                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined     68680838                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses                      64020959                       # ITB accesses
system.cpu.itb.acv                                  0                       # ITB acv
system.cpu.itb.hits                          64020665                       # ITB hits
system.cpu.itb.misses                             294                       # ITB misses
system.cpu.l2cache.ReadExReq_accesses            3195                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency  6098.591549                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency  3098.591549                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency     19485000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses              3195                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency      9900000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses         3195                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses              4877                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency  5592.080378                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2592.080378                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                   647                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency      23654500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.867336                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                4230                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency     10964500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.867336                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses           4230                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses            121                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency  5698.347107                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency  2698.347107                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency       689500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses              121                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency       326500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses          121                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses             636                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits                 636                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.128309                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses               8072                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency  5810.033670                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency  2810.033670                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                    647                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency       43139500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.919846                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                 7425                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency     20864500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.919846                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses            7425                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses              8072                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency  5810.033670                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency  2810.033670                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                   647                       # number of overall hits
system.cpu.l2cache.overall_miss_latency      43139500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.919846                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                7425                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency     20864500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.919846                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses           7425                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements                    15                       # number of replacements
system.cpu.l2cache.sampled_refs                  4684                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse              3884.477480                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                     601                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.numCycles                        269780419                       # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles          8898218                       # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps      259532341                       # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents         1493929                       # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles         138057394                       # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents        7378387                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups      685335905                       # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts       519882318                       # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands    336260549                       # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles           96875532                       # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles        15490881                       # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles       10098203                       # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps          76728208                       # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles       356901                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts        37939                       # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts           22218757                       # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts          251                       # count of temporary serializing insts renamed
system.cpu.timesIdled                             727                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls

---------- End Simulation Statistics   ----------