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gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt

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Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- Begin Simulation Statistics ----------
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_seconds 0.000650 # Number of seconds simulated
sim_ticks 649827000 # Number of ticks simulated
final_tick 649827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
host_tick_rate 87337651 # Simulator tick rate (ticks/s)
host_mem_usage 355516 # Number of bytes of host memory used
host_seconds 7.44 # Real time elapsed on the host
system.physmem.bytes_read::cpu0 81682 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 82403 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 82634 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 80397 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 83903 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 81493 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 81053 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 80348 # Number of bytes read from this memory
system.physmem.bytes_read::total 653913 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 411392 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5164 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5249 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5478 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5343 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5429 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5380 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5399 # Number of bytes written to this memory
system.physmem.bytes_written::total 454226 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 10933 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 11024 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 11066 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 11034 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 11012 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 10870 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 10997 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 10859 # Number of read requests responded to by this memory
system.physmem.num_reads::total 87795 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6428 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5164 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5249 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5478 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5343 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5429 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5380 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5399 # Number of write requests responded to by this memory
system.physmem.num_writes::total 49262 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 125698070 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 126807596 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 127163076 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 123720621 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 129115903 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 125407224 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 124730120 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 123645216 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1006287827 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 633079266 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 8297593 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 7946730 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 8077534 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 8429936 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 8222188 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 8354531 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 8279127 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 8308365 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 698995271 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 633079266 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 133995663 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 134754327 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 135240610 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 132150557 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 137338092 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 133761755 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 133009247 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 131953581 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1705283098 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 1705280021 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 84626 # Transaction distribution
system.membus.trans_dist::ReadResp 84624 # Transaction distribution
system.membus.trans_dist::WriteReq 42834 # Transaction distribution
system.membus.trans_dist::WriteResp 42832 # Transaction distribution
system.membus.trans_dist::Writeback 6428 # Transaction distribution
system.membus.trans_dist::UpgradeReq 56782 # Transaction distribution
system.membus.trans_dist::UpgradeResp 46322 # Transaction distribution
system.membus.trans_dist::ReadExReq 48493 # Transaction distribution
system.membus.trans_dist::ReadExResp 3169 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side 416110 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 416110 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side 1108137 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 1108137 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 1108137 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 287607668 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 44.3 # Layer utilization (%)
system.membus.respLayer0.occupancy 310731500 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 47.8 # Layer utilization (%)
system.l2c.replacements 13443 # number of replacements
system.l2c.tagsinuse 785.847638 # Cycle average of tags in use
system.l2c.total_refs 148477 # Total number of references to valid blocks.
system.l2c.sampled_refs 14254 # Sample count of references to valid blocks.
system.l2c.avg_refs 10.416515 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.occ_blocks::writebacks 727.764026 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0 7.053915 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1 7.581472 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2 7.416719 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3 7.244884 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu4 7.857651 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu5 7.082573 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu6 6.903381 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu7 6.943017 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.710707 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0 0.006889 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1 0.007404 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2 0.007243 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3 0.007075 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu4 0.007673 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu5 0.006917 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu6 0.006742 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu7 0.006780 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.767429 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0 10664 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1 10479 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2 10841 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3 10758 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4 10614 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5 10530 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6 10691 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7 10867 # number of ReadReq hits
system.l2c.ReadReq_hits::total 85444 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 73993 # number of Writeback hits
system.l2c.Writeback_hits::total 73993 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0 363 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 337 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 327 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 310 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 313 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 326 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 344 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 344 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2664 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1821 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1874 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1837 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1846 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1900 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1886 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1867 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1842 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 14873 # number of ReadExReq hits
system.l2c.demand_hits::cpu0 12485 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12353 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12678 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12604 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12514 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12416 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12558 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12709 # number of demand (read+write) hits
system.l2c.demand_hits::total 100317 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12485 # number of overall hits
system.l2c.overall_hits::cpu1 12353 # number of overall hits
system.l2c.overall_hits::cpu2 12678 # number of overall hits
system.l2c.overall_hits::cpu3 12604 # number of overall hits
system.l2c.overall_hits::cpu4 12514 # number of overall hits
system.l2c.overall_hits::cpu5 12416 # number of overall hits
system.l2c.overall_hits::cpu6 12558 # number of overall hits
system.l2c.overall_hits::cpu7 12709 # number of overall hits
system.l2c.overall_hits::total 100317 # number of overall hits
system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1 740 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2 751 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3 714 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4 782 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5 720 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6 737 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7 688 # number of ReadReq misses
system.l2c.ReadReq_misses::total 5877 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0 1987 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 1883 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 1865 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 1791 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 1907 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 1910 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 1895 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 1890 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 15128 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4230 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4311 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4330 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4249 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4286 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4380 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4201 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4403 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 34390 # number of ReadExReq misses
system.l2c.demand_misses::cpu0 4975 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 5051 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5081 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 4963 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5068 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5100 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 4938 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5091 # number of demand (read+write) misses
system.l2c.demand_misses::total 40267 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 4975 # number of overall misses
system.l2c.overall_misses::cpu1 5051 # number of overall misses
system.l2c.overall_misses::cpu2 5081 # number of overall misses
system.l2c.overall_misses::cpu3 4963 # number of overall misses
system.l2c.overall_misses::cpu4 5068 # number of overall misses
system.l2c.overall_misses::cpu5 5100 # number of overall misses
system.l2c.overall_misses::cpu6 4938 # number of overall misses
system.l2c.overall_misses::cpu7 5091 # number of overall misses
system.l2c.overall_misses::total 40267 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0 46342500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1 45732000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2 46640500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3 44232499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4 48395500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5 43931000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6 45019000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7 42654500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 362947499 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0 57720500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 54568500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 56051000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 51373500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 56366000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 55004000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 55764000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 54598000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 441445500 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 227493499 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 232269500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 233545000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 229482499 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 231206500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 236797000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 226713000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 237470499 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1854977497 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0 273835999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 278001500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 280185500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 273714998 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 279602000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 280728000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 271732000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 280124999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2217924996 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 273835999 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 278001500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 280185500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 273714998 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 279602000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 280728000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 271732000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 280124999 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2217924996 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0 11409 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1 11219 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2 11592 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3 11472 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4 11396 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5 11250 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6 11428 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7 11555 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 91321 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 73993 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 73993 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2350 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2220 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2192 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2101 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2220 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2236 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2239 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2234 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 17792 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6051 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6185 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6167 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6095 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6186 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6266 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6068 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6245 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 49263 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 17460 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 17404 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 17759 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 17567 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 17582 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 17516 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 17496 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 17800 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 140584 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 17460 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 17404 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 17759 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 17567 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 17582 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 17516 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 17496 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 17800 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 140584 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0 0.065299 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1 0.065960 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2 0.064786 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3 0.062238 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4 0.068621 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5 0.064000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6 0.064491 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7 0.059541 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.064355 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.845532 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.848198 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.850821 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.852451 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.859009 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.854204 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.846360 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.846016 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.850270 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.699058 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.697009 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.702124 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.697129 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.692855 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.699011 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.692320 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.705044 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.698090 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0 0.284937 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.290221 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.286108 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.282518 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.288249 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.291162 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.282236 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.286011 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.286427 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.284937 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.290221 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.286108 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.282518 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.288249 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.291162 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.282236 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.286011 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.286427 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 62204.697987 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 61800 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 62104.527297 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 61950.278711 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 61886.828645 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 61015.277778 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 61084.124830 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 61997.819767 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 61757.273949 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 29049.068948 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 28979.553903 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 30054.155496 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 28684.254606 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 29557.420031 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 28797.905759 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 29426.912929 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 28887.830688 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 29180.691433 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 53780.969031 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 53878.334493 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 53936.489607 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 54008.590021 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 53944.587028 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 54063.242009 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 53966.436563 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 53933.794913 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53939.444519 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 55042.411859 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 55038.903187 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 55143.770911 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 55151.117872 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 55170.086819 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 55044.705882 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 55028.756582 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 55023.570811 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 55080.462811 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 55042.411859 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 55038.903187 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 55143.770911 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 55151.117872 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 55170.086819 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 55044.705882 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 55028.756582 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 55023.570811 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 55080.462811 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 13397 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.blocked::no_mshrs 1907 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 7.025170 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.writebacks::writebacks 6428 # number of writebacks
system.l2c.writebacks::total 6428 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0 6 # number of ReadReq MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_mshr_hits::cpu1 6 # number of ReadReq MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_hits::cpu2 6 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6 10 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6 3 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 28 # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 6 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 6 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0 739 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1 734 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2 745 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3 710 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4 775 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5 713 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6 727 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7 683 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 5826 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 1986 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 1882 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 1865 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 1791 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 1907 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 1910 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 1894 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 1889 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 15124 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4226 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4305 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4324 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4247 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4284 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4378 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4198 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4400 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 34362 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 4965 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 5039 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5069 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 4957 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5059 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5091 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 4925 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5083 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 40188 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 4965 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 5039 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5069 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 4957 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5059 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5091 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 4925 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5083 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 40188 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0 37216000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1 36653500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2 37301500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3 35511499 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4 38736500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5 34925000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6 35756000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7 34110500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 290210499 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81531000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 77219000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76527500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 73571500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 78291500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 78487500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 77899500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77615500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 621143000 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 176232999 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 179835500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 181021500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 177936499 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 179280500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 183709500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 175748500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 184108999 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1437873997 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 213448999 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 216489000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 218323000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 213447998 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 218017000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 218634500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 211504500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 218219499 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1728084496 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 213448999 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 216489000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 218323000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 213447998 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 218017000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 218634500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 211504500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 218219499 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1728084496 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 406261500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 408851000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 410764500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 410830500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407460500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 403658000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 409230500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 404004500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3261061000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 227401000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 218592500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 221548500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 231869500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 226934000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230334000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226902000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 228628000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1812209500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 633662500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 627443500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 632313000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 642700000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 634394500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 633992000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 636132500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 632632500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 5073270500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064773 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1 0.065425 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064268 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061890 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4 0.068006 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5 0.063378 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063616 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7 0.059109 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.063797 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.845106 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847748 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.850821 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.852451 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.859009 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.854204 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.845913 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.845568 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.850045 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.698397 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.696039 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.701151 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.696801 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.692532 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698691 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.691826 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.704564 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.697521 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.284364 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.289531 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.285433 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.282177 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.287737 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.290649 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.281493 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.285562 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.285865 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.284364 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.289531 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.285433 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.282177 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.287737 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.290649 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.281493 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.285562 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.285865 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50359.945873 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49936.648501 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50069.127517 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50016.195775 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49982.580645 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48983.169705 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49182.943604 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49942.166911 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 49812.993306 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41052.870091 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41030.286929 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41033.512064 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41078.447795 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41054.798112 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41092.931937 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41129.619852 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41088.141874 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41070.021158 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41702.082111 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41773.635308 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41864.361702 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41896.985872 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41848.856209 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41961.968936 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41864.816579 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41842.954318 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41844.886706 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 42990.734945 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 42962.691010 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 43070.230815 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 43059.914868 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 43094.880411 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 42945.295620 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 42945.076142 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 42931.241196 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 43000.012342 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 42990.734945 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 42962.691010 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 43070.230815 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 43059.914868 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 43094.880411 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 42945.295620 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 42945.076142 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 42931.241196 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 43000.012342 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.funcbus.throughput 0 # Throughput (bytes/s)
system.funcbus.data_through_bus 0 # Total data (bytes)
system.toL2Bus.throughput 51050793519 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 365486 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 365476 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 42834 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 42830 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 73993 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 28250 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 28248 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 155786 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 155781 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118183 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 117760 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118671 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 118343 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 117990 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118322 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118461 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 118625 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 946355 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1725217 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1723022 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1747851 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1725043 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1729886 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1731401 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1727521 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1744371 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 13854312 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 13854312 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 19319872 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 649780490 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 156586979 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 156968437 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 157751073 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 24.3 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 157263428 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 24.2 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 156564098 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 157250041 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 24.2 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 157464901 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 24.2 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 157629539 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 24.3 # Layer utilization (%)
system.cpu0.num_reads 98049 # number of read accesses completed
system.cpu0.num_writes 53278 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.num_copies 0 # number of copy accesses completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.l1c.replacements 21910 # number of replacements
system.cpu0.l1c.tagsinuse 394.044184 # Cycle average of tags in use
system.cpu0.l1c.total_refs 13156 # Total number of references to valid blocks.
system.cpu0.l1c.sampled_refs 22301 # Sample count of references to valid blocks.
system.cpu0.l1c.avg_refs 0.589929 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.l1c.occ_blocks::cpu0 394.044184 # Average occupied blocks per requestor
system.cpu0.l1c.occ_percent::cpu0 0.769618 # Average percentage of cache occupancy
system.cpu0.l1c.occ_percent::total 0.769618 # Average percentage of cache occupancy
system.cpu0.l1c.ReadReq_hits::cpu0 8471 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8471 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1074 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1074 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9545 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9545 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9545 # number of overall hits
system.cpu0.l1c.overall_hits::total 9545 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 35640 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 35640 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 23074 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 23074 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 58714 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 58714 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 58714 # number of overall misses
system.cpu0.l1c.overall_misses::total 58714 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 933901812 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 933901812 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 856280361 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 856280361 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1790182173 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1790182173 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1790182173 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1790182173 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 44111 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 44111 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 24148 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 24148 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 68259 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 68259 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 68259 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 68259 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807962 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.807962 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955524 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.955524 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.860165 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.860165 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.860165 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.860165 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26203.754545 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 26203.754545 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37110.182933 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 37110.182933 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.869077 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 30489.869077 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.869077 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 30489.869077 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 1011011 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.l1c.blocked::no_mshrs 61585 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.416514 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.l1c.writebacks::writebacks 9569 # number of writebacks
system.cpu0.l1c.writebacks::total 9569 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35640 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 35640 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23074 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 23074 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 58714 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 58714 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 58714 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 58714 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 860177811 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 860177811 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 808764395 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 808764395 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1668942206 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1668942206 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1668942206 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1668942206 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 696207485 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 696207485 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1651009618 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1651009618 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2347217103 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2347217103 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807962 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807962 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955524 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955524 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860165 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.860165 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860165 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.860165 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24135.179882 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24135.179882 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35050.896897 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35050.896897 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28424.944749 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28424.944749 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28424.944749 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28424.944749 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.num_reads 98391 # number of read accesses completed
system.cpu1.num_writes 53060 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.num_copies 0 # number of copy accesses completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.l1c.replacements 21908 # number of replacements
system.cpu1.l1c.tagsinuse 394.826417 # Cycle average of tags in use
system.cpu1.l1c.total_refs 13138 # Total number of references to valid blocks.
system.cpu1.l1c.sampled_refs 22318 # Sample count of references to valid blocks.
system.cpu1.l1c.avg_refs 0.588673 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.l1c.occ_blocks::cpu1 394.826417 # Average occupied blocks per requestor
system.cpu1.l1c.occ_percent::cpu1 0.771145 # Average percentage of cache occupancy
system.cpu1.l1c.occ_percent::total 0.771145 # Average percentage of cache occupancy
system.cpu1.l1c.ReadReq_hits::cpu1 8563 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8563 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1113 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1113 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9676 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9676 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9676 # number of overall hits
system.cpu1.l1c.overall_hits::total 9676 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 35632 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 35632 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23114 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23114 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 58746 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 58746 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 58746 # number of overall misses
system.cpu1.l1c.overall_misses::total 58746 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 934157803 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 934157803 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 854823705 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 854823705 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1788981508 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1788981508 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1788981508 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1788981508 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 44195 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 44195 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 24227 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 24227 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 68422 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 68422 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 68422 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 68422 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806245 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.806245 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954060 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.954060 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.858583 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.858583 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.858583 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.858583 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26216.822042 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 26216.822042 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 36982.941291 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 36982.941291 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 30452.822456 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 30452.822456 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 30452.822456 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 30452.822456 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 1014678 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.l1c.blocked::no_mshrs 61858 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.403343 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.l1c.writebacks::writebacks 9599 # number of writebacks
system.cpu1.l1c.writebacks::total 9599 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35632 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 35632 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23114 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23114 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 58746 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 58746 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 58746 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 58746 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 860390916 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 860390916 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 807278180 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 807278180 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1667669096 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1667669096 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1667669096 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1667669096 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 703500956 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 703500956 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1594898180 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1594898180 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2298399136 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2298399136 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806245 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806245 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954060 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954060 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858583 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.858583 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858583 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.858583 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24146.579367 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24146.579367 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34925.940123 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34925.940123 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28387.789739 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28387.789739 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28387.789739 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28387.789739 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.num_reads 100000 # number of read accesses completed
system.cpu2.num_writes 53426 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.num_copies 0 # number of copy accesses completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.l1c.replacements 22360 # number of replacements
system.cpu2.l1c.tagsinuse 394.888678 # Cycle average of tags in use
system.cpu2.l1c.total_refs 13327 # Total number of references to valid blocks.
system.cpu2.l1c.sampled_refs 22756 # Sample count of references to valid blocks.
system.cpu2.l1c.avg_refs 0.585648 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.l1c.occ_blocks::cpu2 394.888678 # Average occupied blocks per requestor
system.cpu2.l1c.occ_percent::cpu2 0.771267 # Average percentage of cache occupancy
system.cpu2.l1c.occ_percent::total 0.771267 # Average percentage of cache occupancy
system.cpu2.l1c.ReadReq_hits::cpu2 8771 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8771 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1101 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1101 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9872 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9872 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9872 # number of overall hits
system.cpu2.l1c.overall_hits::total 9872 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36112 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36112 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 22938 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 22938 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 59050 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 59050 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 59050 # number of overall misses
system.cpu2.l1c.overall_misses::total 59050 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 945591370 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 945591370 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 849320343 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 849320343 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1794911713 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1794911713 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1794911713 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1794911713 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 44883 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 44883 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 24039 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 24039 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 68922 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 68922 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 68922 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 68922 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804581 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.804581 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954199 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.954199 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.856766 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.856766 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.856766 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.856766 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26184.962616 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 26184.962616 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37026.782762 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 37026.782762 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 30396.472701 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 30396.472701 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 30396.472701 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 30396.472701 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 1018235 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.l1c.blocked::no_mshrs 62319 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.339078 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.l1c.writebacks::writebacks 9616 # number of writebacks
system.cpu2.l1c.writebacks::total 9616 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36112 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36112 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22938 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 22938 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 59050 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 59050 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 59050 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 59050 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 870903925 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 870903925 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 802151745 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 802151745 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1673055670 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1673055670 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1673055670 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1673055670 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 702585995 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 702585995 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1602698265 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1602698265 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2305284260 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2305284260 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804581 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804581 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954199 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954199 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856766 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.856766 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856766 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.856766 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24116.745819 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24116.745819 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34970.430944 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34970.430944 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28332.864860 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28332.864860 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.num_reads 98539 # number of read accesses completed
system.cpu3.num_writes 53510 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.num_copies 0 # number of copy accesses completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.l1c.replacements 21926 # number of replacements
system.cpu3.l1c.tagsinuse 394.806744 # Cycle average of tags in use
system.cpu3.l1c.total_refs 12847 # Total number of references to valid blocks.
system.cpu3.l1c.sampled_refs 22328 # Sample count of references to valid blocks.
system.cpu3.l1c.avg_refs 0.575376 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.l1c.occ_blocks::cpu3 394.806744 # Average occupied blocks per requestor
system.cpu3.l1c.occ_percent::cpu3 0.771107 # Average percentage of cache occupancy
system.cpu3.l1c.occ_percent::total 0.771107 # Average percentage of cache occupancy
system.cpu3.l1c.ReadReq_hits::cpu3 8426 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8426 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1071 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1071 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9497 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9497 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9497 # number of overall hits
system.cpu3.l1c.overall_hits::total 9497 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 35942 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 35942 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 22767 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 22767 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 58709 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 58709 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 58709 # number of overall misses
system.cpu3.l1c.overall_misses::total 58709 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 940164359 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 940164359 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 841530610 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 841530610 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1781694969 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1781694969 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1781694969 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1781694969 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 44368 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 44368 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 23838 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 23838 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 68206 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 68206 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 68206 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 68206 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.810088 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.810088 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955072 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.955072 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.860760 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.860760 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.860760 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.860760 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26157.819793 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 26157.819793 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36962.735978 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 36962.735978 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 30347.901838 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 30347.901838 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 30347.901838 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 30347.901838 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 1011201 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.l1c.blocked::no_mshrs 61773 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.369628 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu3.l1c.writebacks::writebacks 9447 # number of writebacks
system.cpu3.l1c.writebacks::total 9447 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35942 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 35942 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22767 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 22767 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 58709 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 58709 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 58709 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 58709 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 865819865 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 865819865 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 794633661 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 794633661 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1660453526 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1660453526 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1660453526 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1660453526 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 705869404 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 705869404 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1670668640 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1670668640 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2376538044 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2376538044 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.810088 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.810088 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955072 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955072 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860760 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.860760 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860760 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.860760 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24089.362445 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24089.362445 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34902.870866 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34902.870866 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28282.776508 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28282.776508 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28282.776508 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28282.776508 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu4.num_reads 98567 # number of read accesses completed
system.cpu4.num_writes 53142 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.num_copies 0 # number of copy accesses completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu4.l1c.replacements 21884 # number of replacements
system.cpu4.l1c.tagsinuse 394.848687 # Cycle average of tags in use
system.cpu4.l1c.total_refs 13028 # Total number of references to valid blocks.
system.cpu4.l1c.sampled_refs 22289 # Sample count of references to valid blocks.
system.cpu4.l1c.avg_refs 0.584504 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu4.l1c.occ_blocks::cpu4 394.848687 # Average occupied blocks per requestor
system.cpu4.l1c.occ_percent::cpu4 0.771189 # Average percentage of cache occupancy
system.cpu4.l1c.occ_percent::total 0.771189 # Average percentage of cache occupancy
system.cpu4.l1c.ReadReq_hits::cpu4 8503 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8503 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1105 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1105 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 9608 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 9608 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 9608 # number of overall hits
system.cpu4.l1c.overall_hits::total 9608 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 35561 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 35561 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23022 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23022 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 58583 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 58583 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 58583 # number of overall misses
system.cpu4.l1c.overall_misses::total 58583 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 936314772 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 936314772 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 859386922 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 859386922 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1795701694 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1795701694 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1795701694 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1795701694 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 44064 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 44064 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 24127 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 68191 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 68191 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 68191 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 68191 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807031 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.807031 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954201 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.954201 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.859102 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.859102 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.859102 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.859102 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26329.821209 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 26329.821209 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37328.942837 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 37328.942837 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 30652.265913 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 30652.265913 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 30652.265913 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 30652.265913 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 1016374 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu4.l1c.blocked::no_mshrs 61728 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.465364 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu4.l1c.writebacks::writebacks 9520 # number of writebacks
system.cpu4.l1c.writebacks::total 9520 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35561 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 35561 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23022 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23022 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 58583 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 58583 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 58583 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 58583 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 862769237 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 862769237 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 812030378 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 812030378 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1674799615 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1674799615 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1674799615 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1674799615 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 700729623 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 700729623 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1644067080 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1644067080 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2344796703 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2344796703 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807031 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807031 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954201 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954201 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.859102 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.859102 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24261.669722 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24261.669722 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35271.930241 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35271.930241 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu5.num_reads 98869 # number of read accesses completed
system.cpu5.num_writes 53477 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.num_copies 0 # number of copy accesses completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu5.l1c.replacements 22131 # number of replacements
system.cpu5.l1c.tagsinuse 394.954130 # Cycle average of tags in use
system.cpu5.l1c.total_refs 13197 # Total number of references to valid blocks.
system.cpu5.l1c.sampled_refs 22529 # Sample count of references to valid blocks.
system.cpu5.l1c.avg_refs 0.585778 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu5.l1c.occ_blocks::cpu5 394.954130 # Average occupied blocks per requestor
system.cpu5.l1c.occ_percent::cpu5 0.771395 # Average percentage of cache occupancy
system.cpu5.l1c.occ_percent::total 0.771395 # Average percentage of cache occupancy
system.cpu5.l1c.ReadReq_hits::cpu5 8594 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8594 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1100 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1100 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 9694 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9694 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9694 # number of overall hits
system.cpu5.l1c.overall_hits::total 9694 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 35827 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 35827 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 23090 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 23090 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 58917 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 58917 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 58917 # number of overall misses
system.cpu5.l1c.overall_misses::total 58917 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 936035832 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 936035832 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 858178388 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 858178388 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1794214220 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1794214220 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1794214220 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1794214220 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 44421 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 44421 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 24190 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 24190 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 68611 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 68611 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 68611 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 68611 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806533 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.806533 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954527 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.954527 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.858711 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.858711 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.858711 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.858711 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26126.547911 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 26126.547911 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37166.669034 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 37166.669034 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 30453.251523 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 30453.251523 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 30453.251523 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 30453.251523 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 1010232 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu5.l1c.blocked::no_mshrs 61688 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.376475 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu5.l1c.writebacks::writebacks 9611 # number of writebacks
system.cpu5.l1c.writebacks::total 9611 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35827 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 35827 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23090 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 23090 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 58917 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 58917 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 58917 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 58917 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 861924856 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 861924856 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 810652413 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 810652413 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1672577269 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1672577269 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1672577269 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1672577269 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 694440055 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 694440055 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1653385505 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1653385505 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2347825560 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2347825560 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806533 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806533 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954527 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954527 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858711 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.858711 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858711 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.858711 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24057.969018 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24057.969018 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35108.376483 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35108.376483 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28388.703922 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28388.703922 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28388.703922 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28388.703922 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu6.num_reads 99583 # number of read accesses completed
system.cpu6.num_writes 53438 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.num_copies 0 # number of copy accesses completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu6.l1c.replacements 21939 # number of replacements
system.cpu6.l1c.tagsinuse 394.903585 # Cycle average of tags in use
system.cpu6.l1c.total_refs 13339 # Total number of references to valid blocks.
system.cpu6.l1c.sampled_refs 22346 # Sample count of references to valid blocks.
system.cpu6.l1c.avg_refs 0.596930 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu6.l1c.occ_blocks::cpu6 394.903585 # Average occupied blocks per requestor
system.cpu6.l1c.occ_percent::cpu6 0.771296 # Average percentage of cache occupancy
system.cpu6.l1c.occ_percent::total 0.771296 # Average percentage of cache occupancy
system.cpu6.l1c.ReadReq_hits::cpu6 8764 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8764 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1067 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9831 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9831 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9831 # number of overall hits
system.cpu6.l1c.overall_hits::total 9831 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36046 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36046 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 22895 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 22895 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 58941 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 58941 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 58941 # number of overall misses
system.cpu6.l1c.overall_misses::total 58941 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 938279687 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 938279687 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 845796556 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 845796556 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1784076243 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1784076243 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1784076243 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1784076243 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 44810 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 44810 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 23962 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 23962 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 68772 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 68772 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 68772 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 68772 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804419 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.804419 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955471 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.955471 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.857049 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.857049 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.857049 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.857049 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26030.064002 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 26030.064002 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36942.413453 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 36942.413453 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 30268.849239 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 30268.849239 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 30268.849239 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 30268.849239 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 1009249 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu6.l1c.blocked::no_mshrs 61784 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.335119 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu6.l1c.writebacks::writebacks 9560 # number of writebacks
system.cpu6.l1c.writebacks::total 9560 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36046 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36046 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22895 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 22895 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 58941 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 58941 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 58941 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 58941 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 863686811 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 863686811 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 798668072 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 798668072 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1662354883 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1662354883 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1662354883 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1662354883 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702782954 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702782954 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1637437633 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1637437633 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2340220587 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2340220587 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804419 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804419 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955471 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955471 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857049 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.857049 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857049 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.857049 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 23960.683876 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 23960.683876 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34883.951605 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34883.951605 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28203.710202 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28203.710202 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28203.710202 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28203.710202 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu7.num_reads 99199 # number of read accesses completed
system.cpu7.num_writes 53517 # number of write accesses completed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.num_copies 0 # number of copy accesses completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu7.l1c.replacements 22063 # number of replacements
system.cpu7.l1c.tagsinuse 393.496696 # Cycle average of tags in use
system.cpu7.l1c.total_refs 13289 # Total number of references to valid blocks.
system.cpu7.l1c.sampled_refs 22472 # Sample count of references to valid blocks.
system.cpu7.l1c.avg_refs 0.591358 # Average number of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu7.l1c.occ_blocks::cpu7 393.496696 # Average occupied blocks per requestor
system.cpu7.l1c.occ_percent::cpu7 0.768548 # Average percentage of cache occupancy
system.cpu7.l1c.occ_percent::total 0.768548 # Average percentage of cache occupancy
system.cpu7.l1c.ReadReq_hits::cpu7 8670 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8670 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1128 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1128 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 9798 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9798 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9798 # number of overall hits
system.cpu7.l1c.overall_hits::total 9798 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 35926 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 35926 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23139 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23139 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 59065 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 59065 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 59065 # number of overall misses
system.cpu7.l1c.overall_misses::total 59065 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 933337082 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 933337082 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 860844547 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 860844547 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1794181629 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1794181629 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1794181629 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1794181629 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 44596 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 44596 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 24267 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 24267 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 68863 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 68863 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 68863 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 68863 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805588 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.805588 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953517 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.953517 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.857717 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.857717 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.857717 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.857717 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25979.432222 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 25979.432222 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37203.187130 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 37203.187130 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 30376.392601 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 30376.392601 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 30376.392601 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 30376.392601 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 1011426 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu7.l1c.blocked::no_mshrs 62031 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.305170 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu7.l1c.writebacks::writebacks 9494 # number of writebacks
system.cpu7.l1c.writebacks::total 9494 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35926 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 35926 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23139 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23139 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 59065 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 59065 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 59065 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 59065 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 859043599 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 859043599 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 813252475 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 813252475 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1672296074 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1672296074 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1672296074 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1672296074 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 693959592 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 693959592 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1654672592 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1654672592 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2348632184 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2348632184 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805588 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805588 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953517 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953517 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.857717 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.857717 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23911.473557 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23911.473557 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35146.396776 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35146.396776 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- End Simulation Statistics ----------
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