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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_seconds 47.216814 # Number of seconds simulated
sim_ticks 47216814145000 # Number of ticks simulated
final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
host_inst_rate 919960 # Simulator instruction rate (inst/s)
host_op_rate 1082251 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44530469299 # Simulator tick rate (ticks/s)
host_mem_usage 691012 # Number of bytes of host memory used
host_seconds 1060.33 # Real time elapsed on the host
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_insts 975457230 # Number of instructions simulated
sim_ops 1147538415 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 152064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 126912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3862964 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 62933832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 221952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 220096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2661000 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 46409840 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 419200 # Number of bytes read from this memory
system.physmem.bytes_read::total 117007860 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3862964 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2661000 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6523964 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 100926976 # Number of bytes written to this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bytes_written::total 100947560 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2376 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1983 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 100766 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 983354 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3468 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 3439 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 41685 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 725170 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6550 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1868791 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1576984 # Number of write requests responded to by this memory
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.num_writes::total 1579558 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3221 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2688 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 81813 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1332869 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 4661 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 982909 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8878 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2478097 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 81813 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 138170 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2137522 # Write bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::total 2137958 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2137522 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3221 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2688 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 81813 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1333305 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 4661 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 982909 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8878 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4616055 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.walker.walks 125229 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.read_hits 92662773 # DTB read hits
system.cpu0.dtb.read_misses 88786 # DTB read misses
system.cpu0.dtb.write_hits 85694958 # DTB write hits
system.cpu0.dtb.write_misses 36443 # DTB write misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 92751559 # DTB read accesses
system.cpu0.dtb.write_accesses 85731401 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dtb.hits 178357731 # DTB hits
system.cpu0.dtb.misses 125229 # DTB misses
system.cpu0.dtb.accesses 178482960 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.walker.walks 61377 # Table walker walks requested
system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 497696393 # ITB inst hits
system.cpu0.itb.inst_misses 61377 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses
system.cpu0.itb.hits 497696393 # DTB hits
system.cpu0.itb.misses 61377 # DTB misses
system.cpu0.itb.accesses 497757770 # DTB accesses
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.committedInsts 497466384 # Number of instructions committed
system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses
system.cpu0.num_func_calls 28869117 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls
system.cpu0.num_int_insts 536103359 # number of integer instructions
system.cpu0.num_fp_insts 526132 # number of float instructions
system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read
system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written
system.cpu0.num_mem_refs 178459396 # number of memory refs
system.cpu0.num_load_insts 92737001 # Number of load instructions
system.cpu0.num_store_insts 85722395 # Number of store instructions
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles
system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
system.cpu0.Branches 111287587 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction
system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction
system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction
system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.op_class::total 585300003 # Class of executed instruction
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.replacements 6272771 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.total_refs 172015771 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6273283 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.420375 # Average number of references to valid blocks.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.tag_accesses 363162248 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 363162248 # Number of data accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.WriteReq_hits::cpu0.data 80912298 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 80912298 # number of WriteReq hits
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262024 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 262024 # number of WriteLineReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036634 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 2036634 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 167127209 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 167127209 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 167342863 # number of overall hits
system.cpu0.dcache.overall_hits::total 167342863 # number of overall hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.WriteReq_misses::cpu0.data 1483144 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1483144 # number of WriteReq misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831696 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 831696 # number of WriteLineReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158509 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 158509 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 4792526 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 4792526 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 5564665 # number of overall misses
system.cpu0.dcache.overall_misses::total 5564665 # number of overall misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018000 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.018000 # miss rate for WriteReq accesses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760429 # miss rate for WriteLineReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072209 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072209 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027877 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.027877 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032183 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.032183 # miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.writebacks::writebacks 6272771 # number of writebacks
system.cpu0.dcache.writebacks::total 6272771 # number of writebacks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.replacements 5539081 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits
system.cpu0.icache.overall_hits::total 492212891 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses
system.cpu0.icache.overall_misses::total 5539598 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.icache.writebacks::writebacks 5539081 # number of writebacks
system.cpu0.icache.writebacks::total 5539081 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.tags.replacements 2670833 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16144.496707 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 15583793 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2686790 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 5.800153 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.tags.occ_blocks::writebacks 16059.102143 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 41.665572 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 43.728993 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.980170 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002543 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002669 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.985382 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15907 # Occupied blocks per task id
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1465 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4378 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5313 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4509 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970886 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 397685392 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 397685392 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 298097 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 159313 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 457410 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 4459579 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 4459579 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 7350874 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 7350874 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 760 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 760 # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 635944 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 635944 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5035825 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 5035825 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2962064 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 2962064 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223971 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 223971 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 298097 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 159313 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 5035825 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3598008 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 9091243 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 298097 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 159313 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 5035825 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3598008 # number of overall hits
system.cpu0.l2cache.overall_hits::total 9091243 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11326 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8418 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 19744 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138515 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 138515 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158509 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 158509 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 708286 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 708286 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 503773 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 503773 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1239273 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 1239273 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607364 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 607364 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11326 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8418 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 503773 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1947559 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 2471076 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11326 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8418 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 503773 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1947559 # number of overall misses
system.cpu0.l2cache.overall_misses::total 2471076 # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 309423 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 167731 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 477154 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4459579 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 4459579 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 7350874 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 7350874 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 139275 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 139275 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158509 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 158509 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831335 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 831335 # number of InvalidateReq accesses(hits+misses)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 309423 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 167731 # number of demand (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.l2cache.demand_accesses::cpu0.data 5545567 # number of demand (read+write) accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.demand_accesses::total 11562319 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 309423 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 167731 # number of overall (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.l2cache.overall_accesses::cpu0.data 5545567 # number of overall (read+write) accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.overall_accesses::total 11562319 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050188 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.041379 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994543 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994543 # miss rate for UpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526908 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.526908 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090940 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090940 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294971 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294971 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730589 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730589 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050188 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090940 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.351192 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.213718 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050188 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090940 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.351192 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.213718 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.writebacks::writebacks 1567377 # number of writebacks
system.cpu0.l2cache.writebacks::total 1567377 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.snoop_filter.tot_requests 24282502 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12366009 # Number of requests hitting in the snoop filter with a single holder of the requested data.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.snoop_filter.tot_snoops 1791227 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1790958 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.trans_dist::WritebackDirty 4459579 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 7350874 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 139275 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158509 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 297784 # Transaction distribution
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.trans_dist::InvalidateReq 831335 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 831335 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16703618 # Packet count per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19751529 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.pkt_count::total 37549877 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 709149780 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 756535625 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.pkt_size::total 1470064325 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 6119333 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 30615399 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.066982 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.250025 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.snoop_fanout::0 28565001 93.30% 93.30% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2050129 6.70% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.toL2Bus.snoop_fanout::total 30615399 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.walker.walks 144041 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.read_hits 90153061 # DTB read hits
system.cpu1.dtb.read_misses 111753 # DTB read misses
system.cpu1.dtb.write_hits 81132787 # DTB write hits
system.cpu1.dtb.write_misses 32288 # DTB write misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 90264814 # DTB read accesses
system.cpu1.dtb.write_accesses 81165075 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dtb.hits 171285848 # DTB hits
system.cpu1.dtb.misses 144041 # DTB misses
system.cpu1.dtb.accesses 171429889 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.walker.walks 60885 # Table walker walks requested
system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 478248118 # ITB inst hits
system.cpu1.itb.inst_misses 60885 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses
system.cpu1.itb.hits 478248118 # DTB hits
system.cpu1.itb.misses 60885 # DTB misses
system.cpu1.itb.accesses 478309003 # DTB accesses
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.committedInsts 477990846 # Number of instructions committed
system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses
system.cpu1.num_func_calls 28237407 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls
system.cpu1.num_int_insts 516282159 # number of integer instructions
system.cpu1.num_fp_insts 374678 # number of float instructions
system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read
system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written
system.cpu1.num_mem_refs 171406825 # number of memory refs
system.cpu1.num_load_insts 90251973 # Number of load instructions
system.cpu1.num_store_insts 81154852 # Number of store instructions
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
system.cpu1.Branches 106497601 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction
system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction
system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction
system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.op_class::total 562879339 # Class of executed instruction
system.cpu1.dcache.tags.replacements 5945049 # number of replacements
system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.WriteReq_hits::cpu1.data 76981821 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 76981821 # number of WriteReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63451 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 63451 # number of WriteLineReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048602 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 2048602 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 160679385 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 160679385 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 160867239 # number of overall hits
system.cpu1.dcache.overall_hits::total 160867239 # number of overall hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.WriteReq_misses::cpu1.data 1461655 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1461655 # number of WriteReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427048 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 427048 # number of WriteLineReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 159147 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 159147 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 4819877 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 4819877 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 5612228 # number of overall misses
system.cpu1.dcache.overall_misses::total 5612228 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018633 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.018633 # miss rate for WriteReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870640 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870640 # miss rate for WriteLineReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072086 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072086 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029123 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.029123 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033711 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.033711 # miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.dcache.writebacks::writebacks 5945049 # number of writebacks
system.cpu1.dcache.writebacks::total 5945049 # number of writebacks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.icache.tags.replacements 4741297 # number of replacements
system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits
system.cpu1.icache.overall_hits::total 473560604 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses
system.cpu1.icache.overall_misses::total 4741809 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.icache.writebacks::writebacks 4741297 # number of writebacks
system.cpu1.icache.writebacks::total 4741297 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.tags.replacements 2235881 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13334.612647 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 14249550 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2251891 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 6.327815 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 9713557375000 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 13222.980748 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.246601 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.385297 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.807067 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002823 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003991 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.813880 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1627 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6185 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4247 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3746 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 361919913 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 361919913 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 346945 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153602 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 500547 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 4020160 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 4020160 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 6665818 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 6665818 # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1056 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 1056 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614983 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 614983 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4283593 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 4283593 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3077520 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 3077520 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161463 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 161463 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 346945 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153602 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 4283593 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3692503 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 8476643 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 346945 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153602 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 4283593 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3692503 # number of overall hits
system.cpu1.l2cache.overall_hits::total 8476643 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12460 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9763 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 22223 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 144911 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 144911 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159147 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 159147 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 700907 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 700907 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 458216 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 458216 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1219873 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 1219873 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265383 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 265383 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12460 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9763 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 458216 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1920780 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 2401219 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12460 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9763 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 458216 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1920780 # number of overall misses
system.cpu1.l2cache.overall_misses::total 2401219 # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 359405 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163365 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 522770 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4020160 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 4020160 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 6665818 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 6665818 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145967 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 145967 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 159147 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 159147 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 359405 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163365 # number of demand (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.demand_accesses::total 10877862 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 359405 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163365 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.overall_accesses::total 10877862 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059762 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.042510 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992765 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992765 # miss rate for UpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532649 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532649 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096633 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096633 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283863 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283863 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.621730 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.621730 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059762 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096633 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342185 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.220744 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059762 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096633 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342185 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.220744 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.writebacks::writebacks 1179503 # number of writebacks
system.cpu1.l2cache.writebacks::total 1179503 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.snoop_filter.tot_requests 22049015 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11267078 # Number of requests hitting in the snoop filter with a single holder of the requested data.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 368 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760820 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760650 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4020160 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 6665818 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 145967 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159147 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 305114 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225112 # Packet count per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18660714 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.pkt_count::total 34085270 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 606915272 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 739752124 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.pkt_size::total 1351465172 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 5690396 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 27910438 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.072996 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.260153 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.snoop_fanout::0 25873264 92.70% 92.70% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 2037004 7.30% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.snoop_fanout::total 27910438 # Request fanout histogram
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 136634 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements 115585 # number of replacements
system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.tags.tag_accesses 1040793 # Number of tag accesses
system.iocache.tags.data_accesses 1040793 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.overall_misses::realview.ide 8876 # number of overall misses
system.iocache.overall_misses::total 8916 # number of overall misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.tags.replacements 1759418 # number of replacements
system.l2c.tags.tagsinuse 62296.253449 # Cycle average of tags in use
system.l2c.tags.total_refs 4473392 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1817492 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.461299 # Average number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.tags.occ_blocks::writebacks 34373.643780 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 42.521667 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 58.768031 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3224.697109 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 7016.159468 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 270.222583 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 416.861208 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2985.929949 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 13907.449654 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.524500 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000649 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000897 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.049205 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.107058 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004123 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.006361 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.045562 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.212211 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.950565 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 212 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 57862 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 539 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3515 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5475 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 48284 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.882904 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 73042126 # Number of tag accesses
system.l2c.tags.data_accesses 73042126 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 2746880 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2746880 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 14674 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 12828 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 27502 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 1473 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 1269 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 2742 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 316195 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 262623 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 578818 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4560 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 446108 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 731335 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5573 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3622 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 416632 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 676220 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2290398 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4560 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 446108 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 1047530 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5573 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 3622 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 416632 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 938843 # number of demand (read+write) hits
system.l2c.demand_hits::total 2869216 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4560 # number of overall hits
system.l2c.overall_hits::cpu0.inst 446108 # number of overall hits
system.l2c.overall_hits::cpu0.data 1047530 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5573 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 3622 # number of overall hits
system.l2c.overall_hits::cpu1.inst 416632 # number of overall hits
system.l2c.overall_hits::cpu1.data 938843 # number of overall hits
system.l2c.overall_hits::total 2869216 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 68066 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 63332 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 131398 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 7840 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 7476 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 15316 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 815697 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 546954 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 1362651 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2376 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1983 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 57665 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 181479 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3468 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3439 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 41584 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 187193 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 479187 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2376 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1983 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 57665 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 997176 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3468 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 3439 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 41584 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 734147 # number of demand (read+write) misses
system.l2c.demand_misses::total 1841838 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2376 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1983 # number of overall misses
system.l2c.overall_misses::cpu0.inst 57665 # number of overall misses
system.l2c.overall_misses::cpu0.data 997176 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3468 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 3439 # number of overall misses
system.l2c.overall_misses::cpu1.inst 41584 # number of overall misses
system.l2c.overall_misses::cpu1.data 734147 # number of overall misses
system.l2c.overall_misses::total 1841838 # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks 2746880 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 2746880 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 82740 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 76160 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 158900 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 9313 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 8745 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 18058 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 1131892 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 809577 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 1941469 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8724 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6543 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 503773 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 912814 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9041 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7061 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 458216 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 863413 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 2769585 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 8724 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 6543 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 503773 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 2044706 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 9041 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7061 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 458216 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 1672990 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 4711054 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 8724 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 6543 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 503773 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 2044706 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 9041 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7061 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 458216 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 1672990 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 4711054 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.822649 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831565 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.826923 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.841834 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.854889 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.848156 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.720649 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.675605 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.701866 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303072 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.114466 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.198813 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.487041 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.090752 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.216806 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.173018 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.303072 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.114466 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.487687 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.487041 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.090752 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.438823 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.390961 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.303072 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.114466 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.487687 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.487041 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.090752 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.438823 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.390961 # miss rate for overall accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.writebacks::writebacks 1470290 # number of writebacks
system.l2c.writebacks::total 1470290 # number of writebacks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 82131 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadResp 570231 # Transaction distribution
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.trans_dist::WriteReq 38802 # Transaction distribution
system.membus.trans_dist::WriteResp 38802 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::WritebackDirty 1576984 # Transaction distribution
system.membus.trans_dist::CleanEvict 244820 # Transaction distribution
system.membus.trans_dist::UpgradeReq 347427 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 314914 # Transaction distribution
system.membus.trans_dist::UpgradeResp 168909 # Transaction distribution
system.membus.trans_dist::ReadExReq 1611622 # Transaction distribution
system.membus.trans_dist::ReadExResp 1340459 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 488100 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6542117 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 6692337 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344320 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 344320 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 7036657 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210749660 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 210960657 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.pkt_size::total 218359505 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::samples 4814081 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::1 4814081 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 4814081 # Request fanout histogram
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.toL2Bus.snoop_filter.tot_requests 11103531 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 5720804 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1657088 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 128474 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 115294 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 13180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.toL2Bus.trans_dist::ReadResp 3545235 # Transaction distribution
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.toL2Bus.trans_dist::WritebackDirty 2746880 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1000532 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 352734 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 317656 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 670390 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2212632 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2212632 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 3463102 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9045879 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7635651 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 16681530 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295373981 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 244078084 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 539452065 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1992317 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 13215112 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.283607 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.452956 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.toL2Bus.snoop_fanout::0 9480390 71.74% 71.74% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3721542 28.16% 99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 13180 0.10% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.toL2Bus.snoop_fanout::total 13215112 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink