gem5/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 144806                       # Simulator instruction rate (inst/s)
host_mem_usage                                 206568                       # Number of bytes of host memory used
host_seconds                                 11988.72                       # Real time elapsed on the host
host_tick_rate                               60389347                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                  1736043781                       # Number of instructions simulated
sim_seconds                                  0.723991                       # Number of seconds simulated
sim_ticks                                723991197000                       # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits                297134991                       # Number of BTB hits
system.cpu.BPredUnit.BTBLookups             303959521                       # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect                 162                       # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect           19913428                       # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted          265314839                       # Number of conditional branches predicted
system.cpu.BPredUnit.lookups                344584799                       # Number of BP lookups
system.cpu.BPredUnit.usedRAS                 23886075                       # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches              214632552                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events          63016645                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples   1347786892                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean     1.350199                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev     2.111631                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0    706265401     52.40%     52.40% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1    261524956     19.40%     71.81% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2    126857294      9.41%     81.22% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3     73810788      5.48%     86.69% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4     49267201      3.66%     90.35% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5     31663388      2.35%     92.70% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6     24079219      1.79%     94.49% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7     11302000      0.84%     95.32% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8     63016645      4.68%    100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total   1347786892                       # Number of insts commited each cycle
system.cpu.commit.COM:count                1819780126                       # Number of instructions committed
system.cpu.commit.COM:loads                 444595663                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                  605324165                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts          19912897                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts     1819780126                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts       594069052                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
system.cpu.cpi                               0.834070                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.834070                       # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency        38500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits                2                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency        38500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate     0.333333                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses              1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.333333                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses          521802290                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16279.064598                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10961.675998                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits              511855593                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency   161922923000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.019062                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses              9946697                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits           2670317                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency  79761320000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.013945                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses         7276380                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 27145.945678                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20467.767187                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits             155989397                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency  128647486892                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.029485                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses             4739105                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits          2854288                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency  38577995547                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.011727                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses        1884817                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs  3153.493916                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 30417.808324                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  72.899308                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs             37723                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets           65110                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs    118959251                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets   1980503500                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           682530792                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 19785.804677                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12917.451240                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               667844990                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency    290570409892                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.021517                       # miss rate for demand accesses
system.cpu.dcache.demand_misses              14685802                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits            5524605                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 118339315547                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.013422                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses          9161197                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0                   0.997439                       # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0           4085.509480                       # Average occupied blocks per context
system.cpu.dcache.overall_accesses          682530792                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 19785.804677                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12917.451240                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              667844990                       # number of overall hits
system.cpu.dcache.overall_miss_latency   290570409892                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.021517                       # miss rate for overall accesses
system.cpu.dcache.overall_misses             14685802                       # number of overall misses
system.cpu.dcache.overall_mshr_hits           5524605                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 118339315547                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.013422                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses         9161197                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                9157102                       # number of replacements
system.cpu.dcache.sampled_refs                9161198                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               4085.509480                       # Cycle average of tags in use
system.cpu.dcache.total_refs                667844992                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle             7084078000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                  3077854                       # number of writebacks
system.cpu.decode.DECODE:BlockedCycles       78806586                       # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred            620                       # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved      54720823                       # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts      2797425384                       # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles         722637583                       # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles          541899569                       # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles        88987438                       # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts           1777                       # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles        4443154                       # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses                767802302                       # DTB accesses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_hits                    752449535                       # DTB hits
system.cpu.dtb.data_misses                   15352767                       # DTB misses
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.read_accesses                566812903                       # DTB read accesses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_hits                    557652499                       # DTB read hits
system.cpu.dtb.read_misses                    9160404                       # DTB read misses
system.cpu.dtb.write_accesses               200989399                       # DTB write accesses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_hits                   194797036                       # DTB write hits
system.cpu.dtb.write_misses                   6192363                       # DTB write misses
system.cpu.fetch.Branches                   344584799                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                 354412327                       # Number of cache lines fetched
system.cpu.fetch.Cycles                     911372250                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes               8690810                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                     2851036906                       # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles                28190849                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.237976                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles          354412327                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches          321021066                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        1.968972                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples         1436774330                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.984332                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.873889                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                879814440     61.24%     61.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 48078779      3.35%     64.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 31070380      2.16%     66.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 51055446      3.55%     70.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                122790894      8.55%     78.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 67990825      4.73%     83.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 47151543      3.28%     86.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 36952114      2.57%     89.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                151869909     10.57%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1436774330                       # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses          354412327                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35305.051302                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35462.540717                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits              354411060                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       44731500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                 1267                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits               346                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency     32661000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             921                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               384811.140065                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses           354412327                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35305.051302                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35462.540717                       # average overall mshr miss latency
system.cpu.icache.demand_hits               354411060                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        44731500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
system.cpu.icache.demand_misses                  1267                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                346                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     32661000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              921                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_%::0                   0.352268                       # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0            721.445735                       # Average occupied blocks per context
system.cpu.icache.overall_accesses          354412327                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35305.051302                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35462.540717                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits              354411060                       # number of overall hits
system.cpu.icache.overall_miss_latency       44731500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
system.cpu.icache.overall_misses                 1267                       # number of overall misses
system.cpu.icache.overall_mshr_hits               346                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     32661000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             921                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                      1                       # number of replacements
system.cpu.icache.sampled_refs                    921                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                721.445735                       # Cycle average of tags in use
system.cpu.icache.total_refs                354411060                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                        11208065                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches                280169878                       # Number of branches executed
system.cpu.iew.EXEC:nop                     129057525                       # number of nop insts executed
system.cpu.iew.EXEC:rate                     1.565430                       # Inst execution rate
system.cpu.iew.EXEC:refs                    767802324                       # number of memory reference insts executed
system.cpu.iew.EXEC:stores                  200989407                       # Number of stores executed
system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
system.cpu.iew.WB:consumers                1523016532                       # num instructions consuming a value
system.cpu.iew.WB:count                    2228484684                       # cumulative count of insts written-back
system.cpu.iew.WB:fanout                     0.811571                       # average fanout of values written-back
system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers                1236036667                       # num instructions producing a value
system.cpu.iew.WB:rate                       1.539027                       # insts written-back per cycle
system.cpu.iew.WB:sent                     2249496581                       # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts             21722236                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles                15314374                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts             617102957                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts                 45                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts          21692258                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts            232568585                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts          2603343055                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts             566812917                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          38578662                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts            2266715425                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                 389623                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                 18477                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles               88987438                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                694096                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked       161793                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads        35773426                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses       210663                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation      2851639                       # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads           17                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads    172507294                       # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores     71840083                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents        2851639                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect      3390000                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect       18332236                       # Number of branches that were predicted taken incorrectly
system.cpu.ipc                               1.198940                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.198940                       # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu      1523557218     66.09%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult             93      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd           225      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp            19      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt           139      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult           15      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv            24      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     66.09% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead      577672336     25.06%     91.15% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite     204064018      8.85%    100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total       2305294087                       # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt              13339064                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate             0.005786                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu           3077619     23.07%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     23.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead          8405753     63.02%     86.09% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite         1855692     13.91%    100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples   1436774330                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean     1.604493                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.761639                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0     552319838     38.44%     38.44% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1     267044119     18.59%     57.03% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2     243823244     16.97%     74.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3     135766343      9.45%     83.45% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4     111649965      7.77%     91.22% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5      72620793      5.05%     96.27% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6      43154972      3.00%     99.28% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7       8489654      0.59%     99.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8       1905402      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total   1436774330                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate                     1.592073                       # Inst issue rate
system.cpu.iq.iqInstsAdded                 2474285485                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                2305294087                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                  45                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined       718781925                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued           1290278                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined    318719479                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.fetch_accesses               354412360                       # ITB accesses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_hits                   354412327                       # ITB hits
system.cpu.itb.fetch_misses                        33                       # ITB misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses         1884819                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34457.281872                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31270.548143                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits             1001564                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency  30434566500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate       0.468615                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses            883255                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency  27619868000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.468615                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses       883255                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses           7277300                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34308.231469                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31135.566655                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits               5456738                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency   62460262500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.250170                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses             1820562                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency  56684229500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250170                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses        1820562                       # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses         3077854                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits             3077854                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10339.327830                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  2.807892                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs             1696                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs     17535500                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses            9162119                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34356.921715                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31179.661013                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                6458302                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency    92894829000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.295108                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses              2703817                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency  84304097500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.295108                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses         2703817                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0                  0.484040                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1                  0.327555                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0         15861.025964                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1         10733.328518                       # Average occupied blocks per context
system.cpu.l2cache.overall_accesses           9162119                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34356.921715                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31179.661013                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits               6458302                       # number of overall hits
system.cpu.l2cache.overall_miss_latency   92894829000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.295108                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses             2703817                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency  84304097500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.295108                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses        2703817                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements               2693237                       # number of replacements
system.cpu.l2cache.sampled_refs               2717881                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse             26594.354482                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 7631516                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          148066834500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                 1171784                       # number of writebacks
system.cpu.memDep0.conflictingLoads         123159990                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         64312407                       # Number of conflicting stores.
system.cpu.memDep0.insertedLoads            617102957                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           232568585                       # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles                       1447982395                       # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles         51393371                       # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps     1376202963                       # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents         5887635                       # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles         740841122                       # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents       18541128                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents         493389                       # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups     3535273918                       # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts      2734162916                       # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands   2047681663                       # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles          528076479                       # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles        88987438                       # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles       27475071                       # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps         671478700                       # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles          849                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts           49                       # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts           54007891                       # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts           47                       # count of temporary serializing insts renamed
system.cpu.timesIdled                          425188                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls

---------- End Simulation Statistics   ----------