2006-08-17 00:48:15 +02:00
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|
|
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|
---------- Begin Simulation Statistics ----------
|
2010-09-09 20:40:19 +02:00
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|
|
sim_seconds 0.000032 # Number of seconds simulated
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|
|
|
|
sim_ticks 32088000 # Number of ticks simulated
|
2012-01-25 18:19:50 +01:00
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|
|
final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2011-09-09 10:35:05 +02:00
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|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2012-05-09 20:52:14 +02:00
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|
|
host_inst_rate 273601 # Simulator instruction rate (inst/s)
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|
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|
host_op_rate 273420 # Simulator op (including micro ops) rate (op/s)
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|
host_tick_rate 1504754975 # Simulator tick rate (ticks/s)
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|
host_mem_usage 214572 # Number of bytes of host memory used
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|
|
|
|
host_seconds 0.02 # Real time elapsed on the host
|
2011-09-09 10:35:05 +02:00
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|
|
sim_insts 5827 # Number of instructions simulated
|
2012-02-12 23:07:43 +01:00
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|
|
sim_ops 5827 # Number of ops (including micro ops) simulated
|
2012-01-25 18:19:50 +01:00
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|
|
system.physmem.bytes_read 28096 # Number of bytes read from this memory
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|
system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
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|
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|
system.physmem.bytes_written 0 # Number of bytes written to this memory
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|
|
|
|
system.physmem.num_reads 439 # Number of read requests responded to by this memory
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|
system.physmem.num_writes 0 # Number of write requests responded to by this memory
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|
system.physmem.num_other 0 # Number of other requests responded to by this memory
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|
|
|
|
system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s)
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|
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|
|
system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s)
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|
system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s)
|
2008-02-26 08:20:40 +01:00
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|
|
system.cpu.dtb.read_hits 0 # DTB read hits
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|
|
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|
system.cpu.dtb.read_misses 0 # DTB read misses
|
2011-09-09 10:35:05 +02:00
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|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
2008-02-26 08:20:40 +01:00
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|
|
system.cpu.dtb.write_hits 0 # DTB write hits
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|
|
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
2011-09-09 10:35:05 +02:00
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|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
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|
|
|
|
system.cpu.dtb.hits 0 # DTB hits
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|
|
|
|
system.cpu.dtb.misses 0 # DTB misses
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|
|
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|
system.cpu.dtb.accesses 0 # DTB accesses
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|
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|
system.cpu.itb.read_hits 0 # DTB read hits
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|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
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|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
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|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
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|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
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|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
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|
|
|
|
system.cpu.itb.hits 0 # DTB hits
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|
|
|
|
system.cpu.itb.misses 0 # DTB misses
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|
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
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|
|
|
|
system.cpu.workload.num_syscalls 8 # Number of system calls
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|
|
|
|
system.cpu.numCycles 64176 # number of cpu cycles simulated
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|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-02-12 23:07:43 +01:00
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|
|
system.cpu.committedInsts 5827 # Number of instructions committed
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|
|
|
|
system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
|
2011-09-09 10:35:05 +02:00
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|
|
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
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|
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|
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
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|
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|
|
system.cpu.num_func_calls 194 # number of times a function call or return occured
|
|
|
|
|
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
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|
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|
system.cpu.num_int_insts 5126 # number of integer instructions
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|
system.cpu.num_fp_insts 2 # number of float instructions
|
2011-09-17 18:34:03 +02:00
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|
|
system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
|
2011-09-09 10:35:05 +02:00
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|
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
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|
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
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|
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
|
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|
system.cpu.num_mem_refs 2090 # number of memory refs
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|
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|
system.cpu.num_load_insts 1164 # Number of load instructions
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|
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|
system.cpu.num_store_insts 926 # Number of store instructions
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|
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|
system.cpu.num_idle_cycles 0 # Number of idle cycles
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|
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|
system.cpu.num_busy_cycles 64176 # Number of busy cycles
|
|
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|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
|
|
|
system.cpu.icache.replacements 13 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use
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|
|
system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
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|
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
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|
system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
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|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
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|
|
system.cpu.icache.occ_blocks::cpu.inst 132.493866 # Average occupied blocks per requestor
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|
system.cpu.icache.occ_percent::cpu.inst 0.064694 # Average percentage of cache occupancy
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|
system.cpu.icache.occ_percent::total 0.064694 # Average percentage of cache occupancy
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|
|
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|
system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits
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|
system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits
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|
system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits
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|
system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits
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|
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|
system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits
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|
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|
|
system.cpu.icache.overall_hits::total 5526 # number of overall hits
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|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses
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|
|
|
|
system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses
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|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses
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|
|
|
|
system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses
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|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses
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|
|
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|
system.cpu.icache.overall_misses::total 303 # number of overall misses
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|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles
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|
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|
system.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles
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|
|
system.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles
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|
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|
system.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles
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|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles
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|
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|
system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles
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|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses)
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|
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|
|
system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses)
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|
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|
|
system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses
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|
system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses
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|
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|
|
system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses
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|
|
|
|
system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses
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|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses
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|
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|
system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses
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|
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|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses
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|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-09-09 10:35:05 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-09-09 10:35:05 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
|
2011-09-09 10:35:05 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.021352 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.021352 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 1951 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 138 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
|
2011-09-09 10:35:05 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-09-09 10:35:05 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
2011-09-09 10:35:05 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 54.207742 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004084 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001654 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.005739 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 439 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15652000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 20176000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2652000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2652000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 15652000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 22828000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 15652000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-09-09 10:35:05 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-09-09 10:35:05 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2006-08-18 06:17:21 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
2011-09-09 10:35:05 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-08-17 00:48:15 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
