2012-09-10 19:44:03 +02:00
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Real time: Sep/09/2012 13:47:33
|
2009-05-11 19:38:46 +02:00
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Profiler Stats
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|
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--------------
|
2011-04-20 03:45:23 +02:00
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|
Elapsed_time_in_seconds: 0
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|
Elapsed_time_in_minutes: 0
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|
Elapsed_time_in_hours: 0
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|
Elapsed_time_in_days: 0
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2009-05-11 19:38:46 +02:00
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|
2012-09-10 19:44:03 +02:00
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Virtual_time_in_seconds: 0.42
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|
Virtual_time_in_minutes: 0.007
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|
Virtual_time_in_hours: 0.000116667
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|
Virtual_time_in_days: 4.86111e-06
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2009-05-11 19:38:46 +02:00
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|
2012-09-10 19:44:03 +02:00
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|
Ruby_current_time: 107952
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2010-01-30 05:29:40 +01:00
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Ruby_start_time: 0
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2012-09-10 19:44:03 +02:00
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|
Ruby_cycles: 107952
|
2009-05-11 19:38:46 +02:00
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|
2012-09-10 19:44:03 +02:00
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|
mbytes_resident: 54.2266
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mbytes_total: 273.301
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resident_ratio: 0.198428
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2009-05-11 19:38:46 +02:00
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|
2012-09-10 19:44:03 +02:00
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ruby_cycles_executed: [ 107953 ]
|
2009-05-11 19:38:46 +02:00
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|
Busy Controller Counts:
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|
L1Cache-0:0
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|
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|
|
Directory-0:0
|
2010-01-30 05:29:40 +01:00
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|
|
|
2009-05-11 19:38:46 +02:00
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Busy Bank Count:0
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|
2012-09-10 19:44:03 +02:00
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|
|
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6759 average: 1 | standard deviation: 0 | 0 6759 ]
|
2009-05-11 19:38:46 +02:00
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All Non-Zero Cycle Demand Cache Accesses
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|
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|
----------------------------------------
|
2012-09-10 19:44:03 +02:00
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|
miss_latency: [binsize: 1 max: 125 count: 6758 average: 14.974 | standard deviation: 24.8304 | 0 0 0 5469 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 9 10 284 430 440 7 1 3 10 10 11 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 5 23 35 1 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_LD: [binsize: 1 max: 93 count: 715 average: 37.3343 | standard deviation: 31.1717 | 0 0 0 320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 6 4 94 137 128 1 0 0 4 1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 9 1 ]
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miss_latency_ST: [binsize: 1 max: 125 count: 673 average: 20.0223 | standard deviation: 28.6826 | 0 0 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 43 50 63 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 4 8 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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|
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miss_latency_IFETCH: [binsize: 1 max: 98 count: 5370 average: 11.3641 | standard deviation: 21.4696 | 0 0 0 4655 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 2 5 147 243 249 5 1 2 5 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 3 16 18 0 0 1 0 0 1 ]
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miss_latency_L1Cache: [binsize: 1 max: 3 count: 5469 average: 3 | standard deviation: 0 | 0 0 0 5469 ]
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miss_latency_Directory: [binsize: 1 max: 125 count: 1289 average: 65.7773 | standard deviation: 6.53621 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 9 10 284 430 440 7 1 3 10 10 11 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 5 23 35 1 0 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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2011-02-08 04:23:13 +01:00
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_wCC_Times: 0
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|
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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|
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|
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
2012-09-10 19:44:03 +02:00
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
2011-02-08 04:23:13 +01:00
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imcomplete_dir_Times: 1288
|
2012-09-10 19:44:03 +02:00
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|
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 320 average: 3 | standard deviation: 0 | 0 0 0 320 ]
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miss_latency_LD_Directory: [binsize: 1 max: 93 count: 395 average: 65.1494 | standard deviation: 5.26963 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 6 4 94 137 128 1 0 0 4 1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 9 1 ]
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2011-02-08 04:23:13 +01:00
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miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average: 3 | standard deviation: 0 | 0 0 0 494 ]
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2012-09-10 19:44:03 +02:00
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miss_latency_ST_Directory: [binsize: 1 max: 125 count: 179 average: 67 | standard deviation: 9.07893 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 43 50 63 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 4 8 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4655 average: 3 | standard deviation: 0 | 0 0 0 4655 ]
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miss_latency_IFETCH_Directory: [binsize: 1 max: 98 count: 715 average: 65.8182 | standard deviation: 6.37188 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 2 5 147 243 249 5 1 2 5 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 3 16 18 0 0 1 0 0 1 ]
|
2009-05-11 19:38:46 +02:00
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|
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|
All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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|
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|
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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|
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|
|
Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
|
2010-01-30 05:29:40 +01:00
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|
Total_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ]
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2009-05-11 19:38:46 +02:00
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|
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2010-01-30 05:29:40 +01:00
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|
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1289 average: 0 | standard deviation: 0 | 1289 ]
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|
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|
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1285 average: 0 | standard deviation: 0 | 1285 ]
|
2009-05-11 19:38:46 +02:00
|
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|
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2009-07-07 00:49:48 +02:00
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|
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
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|
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2010-01-30 05:29:40 +01:00
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virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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|
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|
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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|
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virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2009-05-11 19:38:46 +02:00
|
|
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Resource Usage
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--------------
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page_size: 4096
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user_time: 0
|
|
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system_time: 0
|
2012-09-10 19:44:03 +02:00
|
|
|
page_reclaims: 10992
|
2012-05-09 20:52:14 +02:00
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|
|
page_faults: 0
|
2009-05-11 19:38:46 +02:00
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|
swaps: 0
|
2012-05-09 20:52:14 +02:00
|
|
|
block_inputs: 0
|
2012-09-10 19:44:03 +02:00
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block_outputs: 80
|
2009-05-11 19:38:46 +02:00
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|
Network Stats
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-------------
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|
2011-02-08 04:23:13 +01:00
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total_msg_count_Control: 3867 30936
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total_msg_count_Data: 3855 277560
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total_msg_count_Response_Data: 3867 278424
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total_msg_count_Writeback_Control: 3855 30840
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|
total_msgs: 15444 total_bytes: 617760
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|
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|
2009-07-07 00:49:48 +02:00
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|
switch_0_inlinks: 2
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|
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switch_0_outlinks: 2
|
2012-09-10 19:44:03 +02:00
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|
|
links_utilized_percent_switch_0: 5.96098
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links_utilized_percent_switch_0_link_0: 5.96839 bw: 16000 base_latency: 1
|
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|
links_utilized_percent_switch_0_link_1: 5.95357 bw: 16000 base_latency: 1
|
2009-05-11 19:38:46 +02:00
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|
2011-02-08 04:23:13 +01:00
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outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
|
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outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
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2009-05-11 19:38:46 +02:00
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|
2009-07-07 00:49:48 +02:00
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|
switch_1_inlinks: 2
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|
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switch_1_outlinks: 2
|
2012-09-10 19:44:03 +02:00
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links_utilized_percent_switch_1: 5.96098
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links_utilized_percent_switch_1_link_0: 5.95357 bw: 16000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 5.96839 bw: 16000 base_latency: 1
|
2009-05-11 19:38:46 +02:00
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|
2011-02-08 04:23:13 +01:00
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|
outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
|
2009-05-11 19:38:46 +02:00
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switch_2_inlinks: 2
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switch_2_outlinks: 2
|
2012-09-10 19:44:03 +02:00
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|
links_utilized_percent_switch_2: 5.96098
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links_utilized_percent_switch_2_link_0: 5.96839 bw: 16000 base_latency: 1
|
|
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links_utilized_percent_switch_2_link_1: 5.95357 bw: 16000 base_latency: 1
|
2010-01-30 05:29:40 +01:00
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|
2011-02-08 04:23:13 +01:00
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|
outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
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|
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outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
2010-01-30 05:29:40 +01:00
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|
2012-01-25 18:19:50 +01:00
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|
Cache Stats: system.l1_cntrl0.cacheMemory
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|
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|
|
system.l1_cntrl0.cacheMemory_total_misses: 1289
|
|
|
|
|
system.l1_cntrl0.cacheMemory_total_demand_misses: 1289
|
|
|
|
|
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
|
|
|
|
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
|
|
|
|
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2012-01-25 18:19:50 +01:00
|
|
|
system.l1_cntrl0.cacheMemory_request_type_LD: 30.6439%
|
|
|
|
|
system.l1_cntrl0.cacheMemory_request_type_ST: 13.8867%
|
|
|
|
|
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 55.4694%
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2012-01-25 18:19:50 +01:00
|
|
|
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1289 100%
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
--- L1Cache ---
|
2009-05-11 19:38:46 +02:00
|
|
|
- Event Counts -
|
2012-09-10 19:44:03 +02:00
|
|
|
Load [715 ] 715
|
|
|
|
|
Ifetch [5370 ] 5370
|
2011-02-08 04:23:13 +01:00
|
|
|
Store [673 ] 673
|
|
|
|
|
Data [1289 ] 1289
|
|
|
|
|
Fwd_GETX [0 ] 0
|
|
|
|
|
Inv [0 ] 0
|
|
|
|
|
Replacement [1285 ] 1285
|
|
|
|
|
Writeback_Ack [1285 ] 1285
|
|
|
|
|
Writeback_Nack [0 ] 0
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
- Transitions -
|
2011-02-08 04:23:13 +01:00
|
|
|
I Load [395 ] 395
|
|
|
|
|
I Ifetch [715 ] 715
|
|
|
|
|
I Store [179 ] 179
|
|
|
|
|
I Inv [0 ] 0
|
|
|
|
|
I Replacement [0 ] 0
|
|
|
|
|
|
|
|
|
|
II Writeback_Nack [0 ] 0
|
2009-07-07 00:49:48 +02:00
|
|
|
|
2012-09-10 19:44:03 +02:00
|
|
|
M Load [320 ] 320
|
|
|
|
|
M Ifetch [4655 ] 4655
|
2011-02-08 04:23:13 +01:00
|
|
|
M Store [494 ] 494
|
|
|
|
|
M Fwd_GETX [0 ] 0
|
|
|
|
|
M Inv [0 ] 0
|
|
|
|
|
M Replacement [1285 ] 1285
|
2009-07-07 00:49:48 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
MI Fwd_GETX [0 ] 0
|
|
|
|
|
MI Inv [0 ] 0
|
|
|
|
|
MI Writeback_Ack [1285 ] 1285
|
|
|
|
|
MI Writeback_Nack [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
MII Fwd_GETX [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
IS Data [1110 ] 1110
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
IM Data [179 ] 179
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
Memory controller: system.dir_cntrl0.memBuffer:
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_total_requests: 2574
|
|
|
|
|
memory_reads: 1289
|
|
|
|
|
memory_writes: 1285
|
2012-09-10 19:44:03 +02:00
|
|
|
memory_refreshes: 750
|
|
|
|
|
memory_total_request_delays: 1873
|
|
|
|
|
memory_delays_per_request: 0.727661
|
|
|
|
|
memory_delays_in_input_queue: 0
|
|
|
|
|
memory_delays_behind_head_of_bank_queue: 2
|
|
|
|
|
memory_delays_stalled_at_head_of_bank_queue: 1871
|
|
|
|
|
memory_stalls_for_bank_busy: 758
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_random_busy: 0
|
|
|
|
|
memory_stalls_for_anti_starvation: 0
|
2012-09-10 19:44:03 +02:00
|
|
|
memory_stalls_for_arbitration: 69
|
|
|
|
|
memory_stalls_for_bus: 992
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_tfaw: 0
|
2012-09-10 19:44:03 +02:00
|
|
|
memory_stalls_for_read_write_turnaround: 52
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_read_read_turnaround: 0
|
|
|
|
|
accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
--- Directory ---
|
2009-05-11 19:38:46 +02:00
|
|
|
- Event Counts -
|
2011-02-08 04:23:13 +01:00
|
|
|
GETX [1289 ] 1289
|
|
|
|
|
GETS [0 ] 0
|
|
|
|
|
PUTX [1285 ] 1285
|
|
|
|
|
PUTX_NotOwner [0 ] 0
|
|
|
|
|
DMA_READ [0 ] 0
|
|
|
|
|
DMA_WRITE [0 ] 0
|
|
|
|
|
Memory_Data [1289 ] 1289
|
|
|
|
|
Memory_Ack [1285 ] 1285
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
- Transitions -
|
2011-02-08 04:23:13 +01:00
|
|
|
I GETX [1289 ] 1289
|
|
|
|
|
I PUTX_NotOwner [0 ] 0
|
|
|
|
|
I DMA_READ [0 ] 0
|
|
|
|
|
I DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
|
|
M GETX [0 ] 0
|
|
|
|
|
M PUTX [1285 ] 1285
|
|
|
|
|
M PUTX_NotOwner [0 ] 0
|
|
|
|
|
M DMA_READ [0 ] 0
|
|
|
|
|
M DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DRD GETX [0 ] 0
|
|
|
|
|
M_DRD PUTX [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DWR GETX [0 ] 0
|
|
|
|
|
M_DWR PUTX [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DWRI GETX [0 ] 0
|
|
|
|
|
M_DWRI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DRDI GETX [0 ] 0
|
|
|
|
|
M_DRDI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
|
|
IM GETX [0 ] 0
|
|
|
|
|
IM GETS [0 ] 0
|
|
|
|
|
IM PUTX [0 ] 0
|
|
|
|
|
IM PUTX_NotOwner [0 ] 0
|
|
|
|
|
IM DMA_READ [0 ] 0
|
|
|
|
|
IM DMA_WRITE [0 ] 0
|
|
|
|
|
IM Memory_Data [1289 ] 1289
|
|
|
|
|
|
|
|
|
|
MI GETX [0 ] 0
|
|
|
|
|
MI GETS [0 ] 0
|
|
|
|
|
MI PUTX [0 ] 0
|
|
|
|
|
MI PUTX_NotOwner [0 ] 0
|
|
|
|
|
MI DMA_READ [0 ] 0
|
|
|
|
|
MI DMA_WRITE [0 ] 0
|
|
|
|
|
MI Memory_Ack [1285 ] 1285
|
|
|
|
|
|
|
|
|
|
ID GETX [0 ] 0
|
|
|
|
|
ID GETS [0 ] 0
|
|
|
|
|
ID PUTX [0 ] 0
|
|
|
|
|
ID PUTX_NotOwner [0 ] 0
|
|
|
|
|
ID DMA_READ [0 ] 0
|
|
|
|
|
ID DMA_WRITE [0 ] 0
|
|
|
|
|
ID Memory_Data [0 ] 0
|
|
|
|
|
|
|
|
|
|
ID_W GETX [0 ] 0
|
|
|
|
|
ID_W GETS [0 ] 0
|
|
|
|
|
ID_W PUTX [0 ] 0
|
|
|
|
|
ID_W PUTX_NotOwner [0 ] 0
|
|
|
|
|
ID_W DMA_READ [0 ] 0
|
|
|
|
|
ID_W DMA_WRITE [0 ] 0
|
2012-01-25 18:19:50 +01:00
|
|
|
ID_W Memory_Ack [0 ] 0
|
|
|
|
|
|
