2007-04-09 09:59:56 +02:00
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---------- Begin Simulation Statistics ----------
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2011-07-10 19:56:09 +02:00
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sim_seconds 0.000018 # Number of seconds simulated
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sim_ticks 18121000 # Number of ticks simulated
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2007-04-09 09:59:56 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-07-10 19:56:09 +02:00
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host_inst_rate 13353 # Simulator instruction rate (inst/s)
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host_tick_rate 16745708 # Simulator tick rate (ticks/s)
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host_mem_usage 246680 # Number of bytes of host memory used
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host_seconds 1.08 # Real time elapsed on the host
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2008-07-25 01:31:54 +02:00
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sim_insts 14449 # Number of instructions simulated
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2011-06-11 04:15:34 +02:00
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system.cpu.workload.num_syscalls 18 # Number of system calls
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2011-07-10 19:56:09 +02:00
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system.cpu.numCycles 36243 # number of cpu cycles simulated
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2011-06-11 04:15:34 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.lookups 5652 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 3765 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 848 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 5024 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 10750 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 25938 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 5652 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 8192 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2326 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 6715 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 4621 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 374 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 27680 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.937066 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.038861 # Number of instructions fetched each cycle (Total)
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2011-06-11 04:15:34 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::0 19488 70.40% 70.40% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 4056 14.65% 85.06% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 538 1.94% 87.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 473 1.71% 88.71% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 725 2.62% 91.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 641 2.32% 93.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 275 0.99% 94.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 240 0.87% 95.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1244 4.49% 100.00% # Number of instructions fetched each cycle (Total)
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2011-06-11 04:15:34 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::total 27680 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.155947 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.715669 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 11171 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 7401 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 7541 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1378 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 24386 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 1378 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 11668 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 6686 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 7269 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 454 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 22625 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 20272 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 41976 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 41976 # Number of integer rename lookups
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2011-06-11 04:15:34 +02:00
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system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.UndoneMaps 6440 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 639 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 632 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 2436 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 3146 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 2001 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
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2011-06-11 04:15:34 +02:00
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system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.iqInstsAdded 19436 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 18669 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 4953 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 4052 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 27680 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.674458 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.255150 # Number of insts issued each cycle
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2011-06-11 04:15:34 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::0 19155 69.20% 69.20% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 3456 12.49% 81.69% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 2226 8.04% 89.73% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 1550 5.60% 95.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 660 2.38% 97.71% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 386 1.39% 99.11% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle
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2011-06-11 04:15:34 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::total 27680 # Number of insts issued each cycle
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2011-06-11 04:15:34 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available
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2011-06-11 04:15:34 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::IntAlu 13814 73.99% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.99% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 2983 15.98% 89.97% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 1872 10.03% 100.00% # Type of FU issued
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2011-06-11 04:15:34 +02:00
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.FU_type_0::total 18669 # Type of FU issued
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system.cpu.iq.rate 0.515106 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 139 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.007445 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 65238 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 25029 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 17501 # Number of integer instruction queue wakeup accesses
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2011-06-11 04:15:34 +02:00
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system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
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2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 18808 # Number of integer alu accesses
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 920 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 553 # Number of stores squashed
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 1378 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewDispatchedInsts 21162 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 3146 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 2001 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 577 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 948 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 17934 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 2892 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 735 # Number of squashed instructions skipped in execute
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_nop 1111 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 4666 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 3968 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 1774 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.494827 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 17667 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 17501 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 8169 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 9773 # num instructions consuming a value
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_rate 0.482879 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.835874 # average fanout of values written-back
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 5911 # The number of squashed insts skipped by commit
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 848 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 26319 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.576580 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.276701 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 19114 72.62% 72.62% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 4004 15.21% 87.84% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 1216 4.62% 92.46% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 789 3.00% 95.46% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 371 1.41% 96.87% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 322 1.22% 98.09% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 345 1.31% 99.40% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 56 0.21% 99.61% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 102 0.39% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 26319 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.count 15175 # Number of instructions committed
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 3674 # Number of memory references committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.loads 2226 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.commit.branches 3359 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 187 # Number of function calls committed.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.rob.rob_reads 46480 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 43556 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 8563 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.committedInsts 14449 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.cpi 2.508340 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 2.508340 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.398670 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.398670 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 28668 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 15998 # number of integer regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 6298 # number of misc regfile reads
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.tagsinuse 193.254298 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 4159 # Total number of references to valid blocks.
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.avg_refs 12.527108 # Average number of references to valid blocks.
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 193.254298 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.094362 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 4159 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 4159 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 4159 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 462 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 462 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 462 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 16041500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 16041500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 16041500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 4621 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 4621 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 4621 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.099978 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.099978 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.099978 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 34721.861472 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 34721.861472 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 34721.861472 # average overall miss latency
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 130 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 130 # number of overall MSHR hits
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.071846 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.071846 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.071846 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.tagsinuse 102.161362 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 3736 # Total number of references to valid blocks.
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.avg_refs 25.589041 # Average number of references to valid blocks.
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 102.161362 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.024942 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 2696 # number of ReadReq hits
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_hits 3730 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 3730 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_misses 522 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 522 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 3994500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 14649500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 18644000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 18644000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 2810 # number of ReadReq accesses(hits+misses)
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses 4252 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 4252 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.040569 # miss rate for ReadReq accesses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate 0.122766 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.122766 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 35716.475096 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 35716.475096 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
|
2010-10-31 08:07:48 +01:00
|
|
|
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2241500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2985000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 5226500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 5226500 # number of overall MSHR miss cycles
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.022420 # mshr miss rate for ReadReq accesses
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.034337 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.034337 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 228.417094 # Cycle average of tags in use
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 228.417094 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.006971 # Average percentage of cache occupancy
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 393 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 476 # number of overall misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 13475000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2872000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 16347000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 16347000 # number of overall miss cycles
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses)
|
2008-07-25 01:31:54 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.994937 # miss rate for ReadReq accesses
|
2007-08-14 06:16:08 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34287.531807 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34602.409639 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34342.436975 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34342.436975 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 393 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12215000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2608500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 14823500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 14823500 # number of overall MSHR miss cycles
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.424936 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31427.710843 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-06-11 04:15:34 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-04-09 09:59:56 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
