2012-07-11 07:51:55 +02:00
|
|
|
Real time: Jul/10/2012 17:57:35
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
Profiler Stats
|
|
|
|
|
--------------
|
2011-04-20 03:45:23 +02:00
|
|
|
Elapsed_time_in_seconds: 0
|
|
|
|
|
Elapsed_time_in_minutes: 0
|
|
|
|
|
Elapsed_time_in_hours: 0
|
|
|
|
|
Elapsed_time_in_days: 0
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2012-07-11 07:51:55 +02:00
|
|
|
Virtual_time_in_seconds: 0.48
|
|
|
|
|
Virtual_time_in_minutes: 0.008
|
|
|
|
|
Virtual_time_in_hours: 0.000133333
|
|
|
|
|
Virtual_time_in_days: 5.55556e-06
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2010-01-30 05:29:40 +01:00
|
|
|
Ruby_current_time: 253364
|
|
|
|
|
Ruby_start_time: 0
|
|
|
|
|
Ruby_cycles: 253364
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2012-07-11 07:51:55 +02:00
|
|
|
mbytes_resident: 47.7148
|
|
|
|
|
mbytes_total: 237.852
|
|
|
|
|
resident_ratio: 0.200624
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
ruby_cycles_executed: [ 253365 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
Busy Controller Counts:
|
|
|
|
|
L1Cache-0:0
|
|
|
|
|
Directory-0:0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
Busy Bank Count:0
|
|
|
|
|
|
2010-01-30 05:29:40 +01:00
|
|
|
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average: 1 | standard deviation: 0 | 0 6773 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
All Non-Zero Cycle Demand Cache Accesses
|
|
|
|
|
----------------------------------------
|
2010-01-30 05:29:40 +01:00
|
|
|
miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
2011-02-08 04:23:13 +01:00
|
|
|
miss_latency_LD: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
|
|
|
miss_latency_ST: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
2011-04-20 03:45:23 +02:00
|
|
|
miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
2011-02-08 04:23:13 +01:00
|
|
|
miss_latency_L1Cache: [binsize: 1 max: 3 count: 5483 average: 3 | standard deviation: 0 | 0 0 0 5483 ]
|
|
|
|
|
miss_latency_Directory: [binsize: 2 max: 371 count: 1289 average: 178.544 | standard deviation: 22.1923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
|
|
|
|
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
imcomplete_wCC_Times: 0
|
|
|
|
|
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
|
|
|
|
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
|
|
|
|
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
|
|
|
|
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
|
|
|
|
imcomplete_dir_Times: 1288
|
|
|
|
|
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 321 average: 3 | standard deviation: 0 | 0 0 0 321 ]
|
|
|
|
|
miss_latency_LD_Directory: [binsize: 2 max: 285 count: 395 average: 176.514 | standard deviation: 18.6332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
|
|
|
|
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average: 3 | standard deviation: 0 | 0 0 0 494 ]
|
|
|
|
|
miss_latency_ST_Directory: [binsize: 2 max: 371 count: 179 average: 181.905 | standard deviation: 28.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
2011-04-20 03:45:23 +02:00
|
|
|
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average: 3 | standard deviation: 0 | 0 0 0 4668 ]
|
|
|
|
|
miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
All Non-Zero Cycle SW Prefetch Requests
|
|
|
|
|
------------------------------------
|
|
|
|
|
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
Request vs. RubySystem State Profile
|
|
|
|
|
--------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
|
|
|
|
|
Message Delayed Cycles
|
|
|
|
|
----------------------
|
2010-01-30 05:29:40 +01:00
|
|
|
Total_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ]
|
|
|
|
|
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2010-01-30 05:29:40 +01:00
|
|
|
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1289 average: 0 | standard deviation: 0 | 1289 ]
|
|
|
|
|
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1285 average: 0 | standard deviation: 0 | 1285 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2009-07-07 00:49:48 +02:00
|
|
|
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2010-01-30 05:29:40 +01:00
|
|
|
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
|
|
|
|
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
Resource Usage
|
|
|
|
|
--------------
|
|
|
|
|
page_size: 4096
|
|
|
|
|
user_time: 0
|
|
|
|
|
system_time: 0
|
2012-07-11 07:51:55 +02:00
|
|
|
page_reclaims: 13315
|
2012-05-09 20:52:14 +02:00
|
|
|
page_faults: 0
|
2009-05-11 19:38:46 +02:00
|
|
|
swaps: 0
|
2012-05-09 20:52:14 +02:00
|
|
|
block_inputs: 0
|
2012-07-11 07:51:55 +02:00
|
|
|
block_outputs: 0
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
Network Stats
|
|
|
|
|
-------------
|
|
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
total_msg_count_Control: 3867 30936
|
|
|
|
|
total_msg_count_Data: 3855 277560
|
|
|
|
|
total_msg_count_Response_Data: 3867 278424
|
|
|
|
|
total_msg_count_Writeback_Control: 3855 30840
|
|
|
|
|
total_msgs: 15444 total_bytes: 617760
|
|
|
|
|
|
2009-07-07 00:49:48 +02:00
|
|
|
switch_0_inlinks: 2
|
|
|
|
|
switch_0_outlinks: 2
|
2012-01-25 18:19:50 +01:00
|
|
|
links_utilized_percent_switch_0: 2.53982
|
|
|
|
|
links_utilized_percent_switch_0_link_0: 2.54298 bw: 16000 base_latency: 1
|
|
|
|
|
links_utilized_percent_switch_0_link_1: 2.53667 bw: 16000 base_latency: 1
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2009-07-07 00:49:48 +02:00
|
|
|
switch_1_inlinks: 2
|
|
|
|
|
switch_1_outlinks: 2
|
2012-01-25 18:19:50 +01:00
|
|
|
links_utilized_percent_switch_1: 2.53982
|
|
|
|
|
links_utilized_percent_switch_1_link_0: 2.53667 bw: 16000 base_latency: 1
|
|
|
|
|
links_utilized_percent_switch_1_link_1: 2.54298 bw: 16000 base_latency: 1
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
switch_2_inlinks: 2
|
|
|
|
|
switch_2_outlinks: 2
|
2012-01-25 18:19:50 +01:00
|
|
|
links_utilized_percent_switch_2: 2.53982
|
|
|
|
|
links_utilized_percent_switch_2_link_0: 2.54298 bw: 16000 base_latency: 1
|
|
|
|
|
links_utilized_percent_switch_2_link_1: 2.53667 bw: 16000 base_latency: 1
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
|
outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2012-01-25 18:19:50 +01:00
|
|
|
Cache Stats: system.l1_cntrl0.cacheMemory
|
|
|
|
|
system.l1_cntrl0.cacheMemory_total_misses: 1289
|
|
|
|
|
system.l1_cntrl0.cacheMemory_total_demand_misses: 1289
|
|
|
|
|
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
|
|
|
|
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
|
|
|
|
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2012-01-25 18:19:50 +01:00
|
|
|
system.l1_cntrl0.cacheMemory_request_type_LD: 30.6439%
|
|
|
|
|
system.l1_cntrl0.cacheMemory_request_type_ST: 13.8867%
|
|
|
|
|
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 55.4694%
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2012-01-25 18:19:50 +01:00
|
|
|
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1289 100%
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
--- L1Cache ---
|
2009-05-11 19:38:46 +02:00
|
|
|
- Event Counts -
|
2011-02-08 04:23:13 +01:00
|
|
|
Load [716 ] 716
|
|
|
|
|
Ifetch [5383 ] 5383
|
|
|
|
|
Store [673 ] 673
|
|
|
|
|
Data [1289 ] 1289
|
|
|
|
|
Fwd_GETX [0 ] 0
|
|
|
|
|
Inv [0 ] 0
|
|
|
|
|
Replacement [1285 ] 1285
|
|
|
|
|
Writeback_Ack [1285 ] 1285
|
|
|
|
|
Writeback_Nack [0 ] 0
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
- Transitions -
|
2011-02-08 04:23:13 +01:00
|
|
|
I Load [395 ] 395
|
|
|
|
|
I Ifetch [715 ] 715
|
|
|
|
|
I Store [179 ] 179
|
|
|
|
|
I Inv [0 ] 0
|
|
|
|
|
I Replacement [0 ] 0
|
|
|
|
|
|
|
|
|
|
II Writeback_Nack [0 ] 0
|
2009-07-07 00:49:48 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
M Load [321 ] 321
|
|
|
|
|
M Ifetch [4668 ] 4668
|
|
|
|
|
M Store [494 ] 494
|
|
|
|
|
M Fwd_GETX [0 ] 0
|
|
|
|
|
M Inv [0 ] 0
|
|
|
|
|
M Replacement [1285 ] 1285
|
2009-07-07 00:49:48 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
MI Fwd_GETX [0 ] 0
|
|
|
|
|
MI Inv [0 ] 0
|
|
|
|
|
MI Writeback_Ack [1285 ] 1285
|
|
|
|
|
MI Writeback_Nack [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
MII Fwd_GETX [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
IS Data [1110 ] 1110
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
IM Data [179 ] 179
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
Memory controller: system.dir_cntrl0.memBuffer:
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_total_requests: 2574
|
|
|
|
|
memory_reads: 1289
|
|
|
|
|
memory_writes: 1285
|
|
|
|
|
memory_refreshes: 528
|
2012-01-25 18:19:50 +01:00
|
|
|
memory_total_request_delays: 2936
|
|
|
|
|
memory_delays_per_request: 1.14064
|
|
|
|
|
memory_delays_in_input_queue: 668
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_delays_behind_head_of_bank_queue: 3
|
|
|
|
|
memory_delays_stalled_at_head_of_bank_queue: 2265
|
|
|
|
|
memory_stalls_for_bank_busy: 847
|
|
|
|
|
memory_stalls_for_random_busy: 0
|
|
|
|
|
memory_stalls_for_anti_starvation: 0
|
|
|
|
|
memory_stalls_for_arbitration: 88
|
|
|
|
|
memory_stalls_for_bus: 1292
|
|
|
|
|
memory_stalls_for_tfaw: 0
|
|
|
|
|
memory_stalls_for_read_write_turnaround: 38
|
|
|
|
|
memory_stalls_for_read_read_turnaround: 0
|
|
|
|
|
accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
--- Directory ---
|
2009-05-11 19:38:46 +02:00
|
|
|
- Event Counts -
|
2011-02-08 04:23:13 +01:00
|
|
|
GETX [1289 ] 1289
|
|
|
|
|
GETS [0 ] 0
|
|
|
|
|
PUTX [1285 ] 1285
|
|
|
|
|
PUTX_NotOwner [0 ] 0
|
|
|
|
|
DMA_READ [0 ] 0
|
|
|
|
|
DMA_WRITE [0 ] 0
|
|
|
|
|
Memory_Data [1289 ] 1289
|
|
|
|
|
Memory_Ack [1285 ] 1285
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
- Transitions -
|
2011-02-08 04:23:13 +01:00
|
|
|
I GETX [1289 ] 1289
|
|
|
|
|
I PUTX_NotOwner [0 ] 0
|
|
|
|
|
I DMA_READ [0 ] 0
|
|
|
|
|
I DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
|
|
M GETX [0 ] 0
|
|
|
|
|
M PUTX [1285 ] 1285
|
|
|
|
|
M PUTX_NotOwner [0 ] 0
|
|
|
|
|
M DMA_READ [0 ] 0
|
|
|
|
|
M DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DRD GETX [0 ] 0
|
|
|
|
|
M_DRD PUTX [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DWR GETX [0 ] 0
|
|
|
|
|
M_DWR PUTX [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DWRI GETX [0 ] 0
|
|
|
|
|
M_DWRI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DRDI GETX [0 ] 0
|
|
|
|
|
M_DRDI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
|
|
IM GETX [0 ] 0
|
|
|
|
|
IM GETS [0 ] 0
|
|
|
|
|
IM PUTX [0 ] 0
|
|
|
|
|
IM PUTX_NotOwner [0 ] 0
|
|
|
|
|
IM DMA_READ [0 ] 0
|
|
|
|
|
IM DMA_WRITE [0 ] 0
|
|
|
|
|
IM Memory_Data [1289 ] 1289
|
|
|
|
|
|
|
|
|
|
MI GETX [0 ] 0
|
|
|
|
|
MI GETS [0 ] 0
|
|
|
|
|
MI PUTX [0 ] 0
|
|
|
|
|
MI PUTX_NotOwner [0 ] 0
|
|
|
|
|
MI DMA_READ [0 ] 0
|
|
|
|
|
MI DMA_WRITE [0 ] 0
|
|
|
|
|
MI Memory_Ack [1285 ] 1285
|
|
|
|
|
|
|
|
|
|
ID GETX [0 ] 0
|
|
|
|
|
ID GETS [0 ] 0
|
|
|
|
|
ID PUTX [0 ] 0
|
|
|
|
|
ID PUTX_NotOwner [0 ] 0
|
|
|
|
|
ID DMA_READ [0 ] 0
|
|
|
|
|
ID DMA_WRITE [0 ] 0
|
|
|
|
|
ID Memory_Data [0 ] 0
|
|
|
|
|
|
|
|
|
|
ID_W GETX [0 ] 0
|
|
|
|
|
ID_W GETS [0 ] 0
|
|
|
|
|
ID_W PUTX [0 ] 0
|
|
|
|
|
ID_W PUTX_NotOwner [0 ] 0
|
|
|
|
|
ID_W DMA_READ [0 ] 0
|
|
|
|
|
ID_W DMA_WRITE [0 ] 0
|
2012-01-25 18:19:50 +01:00
|
|
|
ID_W Memory_Ack [0 ] 0
|
|
|
|
|
|
