2009-05-12 21:01:17 +02:00
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---------- Begin Simulation Statistics ----------
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2013-01-31 13:49:16 +01:00
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sim_seconds 0.042726 # Number of seconds simulated
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sim_ticks 42726055500 # Number of ticks simulated
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final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2009-05-12 21:01:17 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
|
2013-01-31 13:49:16 +01:00
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host_inst_rate 156388 # Simulator instruction rate (inst/s)
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host_op_rate 156388 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 75637274 # Simulator tick rate (ticks/s)
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host_mem_usage 259292 # Number of bytes of host memory used
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|
host_seconds 564.88 # Real time elapsed on the host
|
2011-02-18 20:31:37 +01:00
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sim_insts 88340673 # Number of instructions simulated
|
2012-02-12 23:07:43 +01:00
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sim_ops 88340673 # Number of ops (including micro ops) simulated
|
2013-01-31 13:49:16 +01:00
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system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory
|
2012-11-02 17:50:06 +01:00
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system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
|
2013-01-31 13:49:16 +01:00
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system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 454848 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 454848 # Number of instructions bytes read from this memory
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2012-10-30 14:35:32 +01:00
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system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
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2013-01-31 13:49:16 +01:00
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system.physmem.num_reads::cpu.inst 7107 # Number of read requests responded to by this memory
|
2012-11-02 17:50:06 +01:00
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system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
|
2013-01-31 13:49:16 +01:00
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system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory
|
2012-10-30 14:35:32 +01:00
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system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
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2013-01-31 13:49:16 +01:00
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system.physmem.bw_read::cpu.inst 10645682 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 237287713 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 247933395 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 10645682 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 10645682 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 170757818 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 170757818 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 170757818 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 10645682 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 237287713 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 165519 # Total number of read requests seen
|
2012-10-30 14:35:32 +01:00
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system.physmem.writeReqs 113997 # Total number of write requests seen
|
2013-01-31 13:49:16 +01:00
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system.physmem.cpureqs 279530 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 10593216 # Total number of bytes read from memory
|
2012-10-30 14:35:32 +01:00
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system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
|
2013-01-31 13:49:16 +01:00
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system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize()
|
2012-10-30 14:35:32 +01:00
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system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
|
2012-11-02 17:50:06 +01:00
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
|
2012-10-25 19:14:42 +02:00
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
|
2013-01-31 13:49:16 +01:00
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system.physmem.perBankRdReqs::0 10574 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 10463 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 10269 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::5 10770 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::9 10444 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::10 10203 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::11 9936 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::12 10514 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis
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|
system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis
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|
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|
system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis
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|
system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis
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|
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|
system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis
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|
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|
system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
2013-01-31 13:49:16 +01:00
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|
|
system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry
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|
system.physmem.totGap 42726035000 # Total gap between requests
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.readPktSize::0 0 # Categorize read packet sizes
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|
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|
|
system.physmem.readPktSize::1 0 # Categorize read packet sizes
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|
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|
|
system.physmem.readPktSize::2 0 # Categorize read packet sizes
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|
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|
|
system.physmem.readPktSize::3 0 # Categorize read packet sizes
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|
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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|
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
2013-01-31 13:49:16 +01:00
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|
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system.physmem.readPktSize::6 165519 # Categorize read packet sizes
|
2012-10-25 19:14:42 +02:00
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|
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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|
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|
|
system.physmem.readPktSize::8 0 # Categorize read packet sizes
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|
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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|
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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|
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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|
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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|
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
|
2013-01-31 13:49:16 +01:00
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|
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system.physmem.writePktSize::6 114011 # categorize write packet sizes
|
2012-10-25 19:14:42 +02:00
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|
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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|
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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|
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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|
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|
|
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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|
|
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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|
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|
|
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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|
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
2013-01-31 13:49:16 +01:00
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system.physmem.rdQLenPdf::0 62480 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 76428 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 18694 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 7913 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
|
2012-10-30 14:35:32 +01:00
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|
|
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
|
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|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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|
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|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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|
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|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
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|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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|
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|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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|
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|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
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|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
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|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
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|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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|
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|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
2013-01-31 13:49:16 +01:00
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system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see
|
2012-11-02 17:50:06 +01:00
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|
|
system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
|
2013-01-31 13:49:16 +01:00
|
|
|
system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see
|
|
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|
|
system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see
|
|
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|
|
system.physmem.wrQLenPdf::8 4956 # What write queue length does an incoming req see
|
2012-10-30 14:35:32 +01:00
|
|
|
system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see
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|
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|
|
system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::12 4956 # What write queue length does an incoming req see
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|
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|
|
system.physmem.wrQLenPdf::13 4956 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::14 4956 # What write queue length does an incoming req see
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|
|
|
|
system.physmem.wrQLenPdf::15 4956 # What write queue length does an incoming req see
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|
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|
|
system.physmem.wrQLenPdf::16 4956 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::17 4956 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::18 4956 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::19 4956 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
|
2013-01-31 13:49:16 +01:00
|
|
|
system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::24 1102 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
|
2013-01-31 13:49:16 +01:00
|
|
|
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
2013-01-31 13:49:16 +01:00
|
|
|
system.physmem.totQLat 7053628221 # Total cycles spent in queuing delays
|
|
|
|
|
system.physmem.totMemAccLat 9647149471 # Sum of mem lat for all requests
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|
|
|
|
system.physmem.totBusLat 827595000 # Total cycles spent in databus access
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|
|
|
|
system.physmem.totBankLat 1765926250 # Total cycles spent in bank access
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|
|
|
|
system.physmem.avgQLat 42615.22 # Average queueing delay per request
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|
|
|
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system.physmem.avgBankLat 10669.02 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 58284.24 # Average memory access latency
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system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
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|
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|
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system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
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|
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system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.27 # Data bus utilization in percentage
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|
system.physmem.avgRdQLen 0.23 # Average read queue length over time
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|
system.physmem.avgWrQLen 10.42 # Average write queue length over time
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|
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|
system.physmem.readRowHits 148856 # Number of row buffer hits during reads
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system.physmem.writeRowHits 71620 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes
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system.physmem.avgGap 152857.21 # Average gap between requests
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|
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|
|
system.cpu.branchPred.lookups 18742591 # Number of BP lookups
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|
system.cpu.branchPred.condPredicted 12317071 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 4774939 # Number of conditional branches incorrect
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|
|
|
system.cpu.branchPred.BTBLookups 15471437 # Number of BTB lookups
|
|
|
|
|
system.cpu.branchPred.BTBHits 4667620 # Number of BTB hits
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.branchPred.BTBHitPct 30.169273 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branchPred.usedRAS 1660963 # Number of times the RAS was used to get a target.
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.read_hits 20277550 # DTB read hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dtb.read_misses 90148 # DTB read misses
|
|
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.read_accesses 20367698 # DTB read accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dtb.write_hits 14728779 # DTB write hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dtb.write_misses 7252 # DTB write misses
|
|
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dtb.write_accesses 14736031 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.data_hits 35006329 # DTB hits
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.dtb.data_misses 97400 # DTB misses
|
|
|
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dtb.data_accesses 35103729 # DTB accesses
|
|
|
|
|
system.cpu.itb.fetch_hits 12368275 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 11063 # ITB misses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.itb.fetch_accesses 12379338 # ITB accesses
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.numCycles 85452112 # number of cpu cycles simulated
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.branch_predictor.predictedTaken 8078019 # Number of Branches Predicted As Taken (True).
|
|
|
|
|
system.cpu.branch_predictor.predictedNotTaken 10664572 # Number of Branches Predicted As Not Taken (False).
|
|
|
|
|
system.cpu.regfile_manager.intRegFileReads 74169588 # Number of Reads from Int. Register File
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.regfile_manager.intRegFileAccesses 126488838 # Total Accesses (Read+Write) to the Int. Register File
|
|
|
|
|
system.cpu.regfile_manager.floatRegFileReads 66061 # Number of Reads from FP Register File
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.regfile_manager.floatRegFileAccesses 293691 # Total Accesses (Read+Write) to the FP Register File
|
|
|
|
|
system.cpu.regfile_manager.regForwards 14166165 # Number of Registers Read Through Forwarding Logic
|
|
|
|
|
system.cpu.agen_unit.agens 35060657 # Number of Address Generations
|
|
|
|
|
system.cpu.execution_unit.predictedTakenIncorrect 4447555 # Number of Branches Incorrectly Predicted As Taken.
|
|
|
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 216884 # Number of Branches Incorrectly Predicted As Not Taken).
|
|
|
|
|
system.cpu.execution_unit.mispredicted 4664439 # Number of Branches Incorrectly Predicted
|
|
|
|
|
system.cpu.execution_unit.predicted 9108157 # Number of Branches Incorrectly Predicted
|
|
|
|
|
system.cpu.execution_unit.mispredictPct 33.867537 # Percentage of Incorrect Branches Predicts
|
|
|
|
|
system.cpu.execution_unit.executions 44777871 # Number of Instructions Executed.
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
|
|
|
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.threadCycles 77185122 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.timesIdled 229327 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed
|
|
|
|
|
system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed.
|
|
|
|
|
system.cpu.activity 81.422683 # Percentage of cycles cpu is active
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.comLoads 20276638 # Number of Load instructions committed
|
|
|
|
|
system.cpu.comStores 14613377 # Number of Store instructions committed
|
|
|
|
|
system.cpu.comBranches 13754477 # Number of Branches instructions committed
|
|
|
|
|
system.cpu.comNops 8748916 # Number of Nop instructions committed
|
|
|
|
|
system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
|
|
|
|
|
system.cpu.comInts 30791227 # Number of Integer instructions committed
|
|
|
|
|
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
|
|
|
|
|
system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread)
|
|
|
|
|
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
|
|
|
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
|
|
|
|
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.cpi 0.967302 # CPI: Cycles Per Instruction (Per-Thread)
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.cpi_total 0.967302 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.033803 # IPC: Instructions Per Cycle (Per-Thread)
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.ipc_total 1.033803 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.stage0.idleCycles 32797293 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage0.runCycles 52654819 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage0.utilization 61.619096 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage1.idleCycles 42999337 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage1.runCycles 42452775 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage1.utilization 49.680194 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage2.idleCycles 42422406 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage2.runCycles 43029706 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage2.utilization 50.355345 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage3.idleCycles 63339640 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage3.runCycles 22112472 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage3.utilization 25.877034 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.stage4.idleCycles 39402909 # Number of cycles 0 instructions are processed.
|
|
|
|
|
system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed.
|
|
|
|
|
system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts).
|
|
|
|
|
system.cpu.icache.replacements 84308 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1908.296965 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks.
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 1908.296965 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 12251160 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 12251160 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 12251160 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 12251160 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 12251160 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 117106 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 117106 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 117106 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 117106 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1888398500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 1888398500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1888398500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 1888398500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1888398500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 1888398500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 12368266 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 12368266 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 12368266 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16125.548648 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 16125.548648 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 16125.548648 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 16125.548648 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 18.066667 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30752 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 30752 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 30752 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 30752 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 30752 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 30752 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86354 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 86354 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 86354 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 86354 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336296000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 1336296000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336296000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 1336296000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336296000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 1336296000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006982 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15474.627695 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15474.627695 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.replacements 131595 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 30966.013927 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 151363 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.924896 # Average number of references to valid blocks.
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 27281.106507 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2018.513793 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 1666.393626 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.832553 # Average percentage of cache occupancy
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.945008 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 79247 # number of ReadReq hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 33054 # number of ReadReq hits
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits::total 112301 # number of ReadReq hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 168350 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 168350 # number of Writeback hits
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 79247 # number of demand (read+write) hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 45933 # number of demand (read+write) hits
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_hits::total 125180 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 79247 # number of overall hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 45933 # number of overall hits
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.overall_hits::total 125180 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 7107 # number of ReadReq misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 27521 # number of ReadReq misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.ReadReq_misses::total 34628 # number of ReadReq misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 130891 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 130891 # number of ReadExReq misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 7107 # number of demand (read+write) misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 158412 # number of demand (read+write) misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_misses::total 165519 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 7107 # number of overall misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.overall_misses::total 165519 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 454675000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513576000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1968251000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996247000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 11996247000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 454675000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 13509823000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 13964498000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 454675000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 13509823000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 13964498000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses)
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 168350 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 168350 # number of Writeback accesses(hits+misses)
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 86354 # number of demand (read+write) accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 204345 # number of demand (read+write) accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::total 290699 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 86354 # number of overall (read+write) accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 204345 # number of overall (read+write) accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.overall_accesses::total 290699 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082301 # miss rate for ReadReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454329 # miss rate for ReadReq accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.235678 # miss rate for ReadReq accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082301 # miss rate for demand accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.569383 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 63975.657802 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54997.129465 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 56839.869470 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91650.663529 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91650.663529 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 84367.945674 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 84367.945674 # average overall miss latency
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2009-05-12 21:01:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2009-05-12 21:01:17 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 113997 # number of writebacks
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7107 # number of ReadReq MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7107 # number of demand (read+write) MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 165519 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7107 # number of overall MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366278633 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1171229430 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537508063 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407065579 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407065579 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366278633 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578295009 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11944573642 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366278633 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578295009 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 11944573642 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for demand accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.569383 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for overall accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51537.728015 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42557.662512 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44400.718003 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79509.405375 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79509.405375 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency
|
2011-06-20 03:43:42 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.replacements 200249 # number of replacements
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 33754882 # Total number of references to valid blocks.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks.
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.avg_refs 165.185750 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 253407000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4078.188712 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.995652 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.995652 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 20180269 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 20180269 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 13574613 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 13574613 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 33754882 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 33754882 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 33754882 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 33754882 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 96369 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 96369 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1038764 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 1038764 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1135133 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 1135133 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3868219500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3868219500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 76703201000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 76703201000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 80571420500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 80571420500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 80571420500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 80571420500 # number of overall miss cycles
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.666283 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.666283 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73840.834877 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 73840.834877 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 70979.718236 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 70979.718236 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 5030029 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.221477 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 168350 # number of writebacks
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35604 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 35604 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895184 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 895184 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 930788 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 930788 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 930788 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 930788 # number of overall MSHR hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 204345 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908697000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908697000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268407000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268407000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14177104000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 14177104000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14177104000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 14177104000 # number of overall MSHR miss cycles
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31411.124825 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31411.124825 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85446.489762 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85446.489762 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2009-05-12 21:01:17 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
