2007-06-22 21:06:10 +02:00
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---------- Begin Simulation Statistics ----------
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2012-02-13 19:30:30 +01:00
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sim_seconds 0.388554 # Number of seconds simulated
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sim_ticks 388554296500 # Number of ticks simulated
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final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2007-06-22 21:06:10 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-05-09 20:52:14 +02:00
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host_inst_rate 119684 # Simulator instruction rate (inst/s)
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host_op_rate 120061 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 33188741 # Simulator tick rate (ticks/s)
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host_mem_usage 223864 # Number of bytes of host memory used
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host_seconds 11707.41 # Real time elapsed on the host
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2012-02-12 23:07:43 +01:00
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sim_insts 1401188958 # Number of instructions simulated
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sim_ops 1405604152 # Number of ops (including micro ops) simulated
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2012-02-13 19:30:30 +01:00
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system.physmem.bytes_read 5987456 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 85056 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 3788160 # Number of bytes written to this memory
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system.physmem.num_reads 93554 # Number of read requests responded to by this memory
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system.physmem.num_writes 59190 # Number of write requests responded to by this memory
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2012-01-25 18:19:50 +01:00
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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2012-02-13 19:30:30 +01:00
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system.physmem.bw_read 15409574 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 218904 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 9749371 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 25158945 # Total bandwidth to/from this memory (bytes/s)
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 49 # Number of system calls
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2012-02-13 19:30:30 +01:00
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system.cpu.numCycles 777108594 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-02-13 19:30:30 +01:00
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system.cpu.BPredUnit.lookups 98192290 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 88412741 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3784661 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 66025458 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 65664289 # Number of BTB hits
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2012-02-13 19:30:30 +01:00
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system.cpu.BPredUnit.usedRAS 1392 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 307 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 165888791 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1648818264 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 98192290 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 65665681 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 330417282 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 21685615 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 262756820 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 2717 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 162823525 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 752138 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 776762747 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.128564 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.147845 # Number of instructions fetched each cycle (Total)
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2009-07-07 00:49:48 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2012-02-13 19:30:30 +01:00
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system.cpu.fetch.rateDist::0 446345465 57.46% 57.46% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 74375625 9.58% 67.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 37980087 4.89% 71.93% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 9083330 1.17% 73.10% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 28159964 3.63% 76.72% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 18826619 2.42% 79.15% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 11515688 1.48% 80.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3871202 0.50% 81.13% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 146604767 18.87% 100.00% # Number of instructions fetched each cycle (Total)
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2009-07-07 00:49:48 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2012-02-13 19:30:30 +01:00
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system.cpu.fetch.rateDist::total 776762747 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.126356 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.121735 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 217443439 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 213446803 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 285373546 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 42801949 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 17697010 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 1642584513 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 17697010 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 241484414 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 36505924 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 52170824 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 303041095 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 125863480 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 1631270043 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 30873302 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 72930971 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 3136079 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 1360952247 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 2755876290 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 2721902713 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 33973577 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed
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2012-02-13 19:30:30 +01:00
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system.cpu.rename.UndoneMaps 116181795 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 2680713 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 2696169 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 271856221 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 438705092 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 180250261 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 255265663 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 83296081 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 1517040384 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 2636529 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1460865188 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 67073 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 113729678 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 136677669 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 392858 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 776762747 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.880710 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.430803 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2012-02-13 19:30:30 +01:00
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system.cpu.iq.issued_per_cycle::0 147116911 18.94% 18.94% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 184456460 23.75% 42.69% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 210881862 27.15% 69.84% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 131212379 16.89% 86.73% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 70768732 9.11% 95.84% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 20345025 2.62% 98.46% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 7834706 1.01% 99.47% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 3973798 0.51% 99.98% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 172874 0.02% 100.00% # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2012-02-13 19:30:30 +01:00
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system.cpu.iq.issued_per_cycle::total 776762747 # Number of insts issued each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2012-02-13 19:30:30 +01:00
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system.cpu.iq.fu_full::IntAlu 106719 6.05% 6.05% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 167382 9.50% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.55% # attempts to use FU when none available
|
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.55% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.55% # attempts to use FU when none available
|
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1159607 65.79% 81.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 328958 18.66% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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|
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
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|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2012-02-13 19:30:30 +01:00
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|
|
system.cpu.iq.FU_type_0::IntAlu 867175983 59.36% 59.36% # Type of FU issued
|
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued
|
|
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|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued
|
|
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|
system.cpu.iq.FU_type_0::FloatAdd 2649316 0.18% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued
|
|
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued
|
|
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued
|
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued
|
|
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued
|
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued
|
|
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|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued
|
|
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|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued
|
|
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|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued
|
|
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|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued
|
|
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|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued
|
|
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|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued
|
|
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued
|
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 419771639 28.73% 88.28% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 171268250 11.72% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 1460865188 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.879873 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 1762666 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 3682454836 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 1624473314 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1444449939 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 17868026 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 9170759 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 8547404 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 1453439561 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 9188293 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 215395742 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 36192248 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 54154 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 246172 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 13402119 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3683 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 46778 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 17697010 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 2543877 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 131664 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 1613864484 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 4125995 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 438705092 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 180250261 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 2550339 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 45235 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 9141 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 246172 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 2357197 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1561193 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 3918390 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1455317466 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 417050361 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 5547722 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.exec_nop 94187571 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 587627055 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 89112581 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 170576694 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.872734 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1453915806 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1452997343 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1154378236 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 1205398776 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.wb_rate 1.869748 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.957673 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 124237250 # The number of squashed insts skipped by commit
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.branchMispredicts 3784661 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 759066348 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.962310 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.504596 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 240497837 31.68% 31.68% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 276436046 36.42% 68.10% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 43137006 5.68% 73.78% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 54981228 7.24% 81.03% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 19702278 2.60% 83.62% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 13356697 1.76% 85.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 30450827 4.01% 89.39% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 10463438 1.38% 90.77% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 70040991 9.23% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 759066348 # Number of insts commited each cycle
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.commit.committedInsts 1485108101 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 569360986 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 402512844 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 51356 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 86248929 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions.
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.bw_lim_events 70040991 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.rob.rob_reads 2302721032 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 3245242057 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 11126 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 345847 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.committedInsts 1401188958 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.cpi 0.554607 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.554607 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.803080 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.803080 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 1980619731 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1276281052 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 16978878 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 10499994 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 593300909 # number of misc regfile reads
|
2011-12-01 00:57:11 +01:00
|
|
|
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.replacements 200 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1048.828471 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 162821549 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 120519.281273 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 1048.828471 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.512123 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.512123 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 162821549 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 162821549 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 162821549 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 162821549 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 162821549 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 162821549 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1976 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 1976 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 1976 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 1976 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 1976 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 1976 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 67232500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 67232500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 67232500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 67232500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 67232500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 67232500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 162823525 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 162823525 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 162823525 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 162823525 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 624 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 624 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 624 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 624 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 624 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1352 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1352 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1352 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 1352 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1352 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 1352 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47023000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 47023000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47023000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 47023000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.replacements 458031 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 365778673 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 462127 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 791.511150 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 131565000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4095.115790 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 200803152 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 200803152 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 164974202 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 164974202 # number of WriteReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
|
|
|
|
|
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 365777354 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 365777354 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 365777354 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 365777354 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 803342 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 803342 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1872614 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 1872614 # number of WriteReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
|
|
|
|
|
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 2675956 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 2675956 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 2675956 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 2675956 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11885207000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 11885207000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 29671016952 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 29671016952 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_miss_latency::cpu.data 267000 # number of SwapReq miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_miss_latency::total 267000 # number of SwapReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 41556223952 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 41556223952 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 41556223952 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 41556223952 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 201606494 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 201606494 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 368453310 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 368453310 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 413195 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603294 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 603294 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1610542 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1610542 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2213836 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 2213836 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2213836 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 2213836 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200048 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 200048 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262072 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 262072 # number of WriteReq MSHR misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 462120 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 462120 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 462120 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 462120 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1554226000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1554226000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3602715222 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3602715222 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 246000 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::total 246000 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5156941222 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.replacements 75325 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 440162 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 90846 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 4.845145 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 15764.439855 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 99.157433 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 1969.677084 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.481093 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.003026 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.060110 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.544228 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 167881 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 167904 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 413195 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 413195 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 202021 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 202021 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 369902 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 369925 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 369902 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 369925 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 1329 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 32167 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 33496 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 60058 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 60058 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1329 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 92225 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 93554 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1329 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 92225 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 93554 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1094618000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1140120500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2066673500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2066673500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 45502500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 3161291500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 3206794000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 45502500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 3161291500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 3206794000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1352 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 200048 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 201400 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 413195 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 413195 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 262079 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 262079 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1352 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 462127 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 463479 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1352 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 462127 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982988 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.160796 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.229160 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982988 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199566 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982988 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199566 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34238.148984 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34029.222495 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34411.294082 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 59190 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 59190 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1329 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32167 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 33496 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60058 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 60058 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1329 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 92225 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 93554 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1329 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 92225 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 93554 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41203500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 997353500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1038557000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1880936000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1880936000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41203500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2878289500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 2919493000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41203500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-06-22 21:06:10 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
