2015-03-19 09:06:20 +01:00
---------- Begin Simulation Statistics ----------
2016-02-10 10:08:27 +01:00
sim_seconds 2.783855 # Number of seconds simulated
2016-07-21 18:19:18 +02:00
sim_ticks 2783855034000 # Number of ticks simulated
final_tick 2783855034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2015-03-19 09:06:20 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-08-02 12:34:32 +02:00
host_inst_rate 850769 # Simulator instruction rate (inst/s)
host_op_rate 1035674 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 16588804734 # Simulator tick rate (ticks/s)
host_mem_usage 576284 # Number of bytes of host memory used
host_seconds 167.82 # Real time elapsed on the host
2016-07-21 18:19:18 +02:00
sim_insts 142771937 # Number of instructions simulated
sim_ops 173801895 # Number of ops (including micro ops) simulated
2015-04-03 18:42:11 +02:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-04-03 18:42:11 +02:00
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory
2016-07-21 18:19:18 +02:00
system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory
2015-04-03 18:42:11 +02:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-07-21 18:19:18 +02:00
system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory
2015-07-03 16:15:03 +02:00
system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory
2016-02-10 10:08:27 +01:00
system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory
2015-04-03 18:42:11 +02:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
2016-02-10 10:08:27 +01:00
system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory
2015-04-03 18:42:11 +02:00
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory
2016-07-21 18:19:18 +02:00
system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory
2015-04-03 18:42:11 +02:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-07-21 18:19:18 +02:00
system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory
2016-02-10 10:08:27 +01:00
system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory
2015-04-03 18:42:11 +02:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
2016-02-10 10:08:27 +01:00
system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory
2015-04-03 18:42:11 +02:00
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
2016-02-10 10:08:27 +01:00
system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_read::cpu.data 3708850 # Total read bandwidth from this memory (bytes/s)
2015-04-03 18:42:11 +02:00
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_read::total 4142977 # Total read bandwidth from this memory (bytes/s)
2016-02-10 10:08:27 +01:00
system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s)
2015-04-03 18:42:11 +02:00
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_write::total 3182092 # Write bandwidth from this memory (bytes/s)
2016-02-10 10:08:27 +01:00
system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s)
2015-04-03 18:42:11 +02:00
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
2016-02-10 10:08:27 +01:00
system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_total::cpu.data 3715145 # Total bandwidth to/from this memory (bytes/s)
2015-04-03 18:42:11 +02:00
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_total::total 7325070 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-04-03 18:42:11 +02:00
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-03-19 09:06:20 +01:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2015-04-03 18:42:11 +02:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
2015-03-19 09:06:20 +01:00
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
2015-04-03 18:42:11 +02:00
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
2015-03-19 09:06:20 +01:00
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2015-04-03 18:42:11 +02:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-04-03 18:42:11 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
2015-03-19 09:06:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2015-04-03 18:42:11 +02:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
2015-03-19 09:06:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
2015-04-03 18:42:11 +02:00
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2016-02-10 10:08:27 +01:00
system.cpu.dtb.walker.walks 10028 # Table walker walks requested
system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency
2015-04-03 18:42:11 +02:00
system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
2016-02-10 10:08:27 +01:00
system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated
2015-03-19 09:06:20 +01:00
system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated
2016-02-10 10:08:27 +01:00
system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst
2015-03-19 09:06:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst
2015-03-19 09:06:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
2015-04-03 18:42:11 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2016-07-21 18:19:18 +02:00
system.cpu.dtb.read_hits 31526014 # DTB read hits
2016-02-10 10:08:27 +01:00
system.cpu.dtb.read_misses 8580 # DTB read misses
2016-07-21 18:19:18 +02:00
system.cpu.dtb.write_hits 23124171 # DTB write hits
2015-03-19 09:06:20 +01:00
system.cpu.dtb.write_misses 1448 # DTB write misses
2015-04-03 18:42:11 +02:00
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-06-21 17:42:04 +02:00
system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB
2015-04-03 18:42:11 +02:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
2016-07-21 18:19:18 +02:00
system.cpu.dtb.read_accesses 31534594 # DTB read accesses
system.cpu.dtb.write_accesses 23125619 # DTB write accesses
2015-04-03 18:42:11 +02:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2016-07-21 18:19:18 +02:00
system.cpu.dtb.hits 54650185 # DTB hits
2016-02-10 10:08:27 +01:00
system.cpu.dtb.misses 10028 # DTB misses
2016-07-21 18:19:18 +02:00
system.cpu.dtb.accesses 54660213 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-04-03 18:42:11 +02:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
2015-03-19 09:06:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2015-04-03 18:42:11 +02:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
2015-03-19 09:06:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
2015-04-03 18:42:11 +02:00
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-04-03 18:42:11 +02:00
system.cpu.itb.walker.walks 4762 # Table walker walks requested
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
2015-03-19 09:06:20 +01:00
system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu.itb.inst_hits 147038452 # ITB inst hits
2015-04-03 18:42:11 +02:00
system.cpu.itb.inst_misses 4762 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
2015-03-19 09:06:20 +01:00
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2015-04-03 18:42:11 +02:00
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-06-21 17:42:04 +02:00
system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
2015-04-03 18:42:11 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2016-07-21 18:19:18 +02:00
system.cpu.itb.inst_accesses 147043214 # ITB inst accesses
system.cpu.itb.hits 147038452 # DTB hits
2015-04-03 18:42:11 +02:00
system.cpu.itb.misses 4762 # DTB misses
2016-07-21 18:19:18 +02:00
system.cpu.itb.accesses 147043214 # DTB accesses
2016-06-06 18:16:44 +02:00
system.cpu.numPwrStateTransitions 6160 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateClkGateDist::mean 874939595.358117 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 17329944407.298908 # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateResidencyTicks::ON 89041080297 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813953703 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5567713149 # number of cpu cycles simulated
2015-03-19 09:06:20 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
2015-04-03 18:42:11 +02:00
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2016-02-10 10:08:27 +01:00
system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
2016-07-21 18:19:18 +02:00
system.cpu.committedInsts 142771937 # Number of instructions committed
system.cpu.committedOps 173801895 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 153161571 # Number of integer alu accesses
2015-03-19 09:06:20 +01:00
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
2016-07-21 18:19:18 +02:00
system.cpu.num_func_calls 16873976 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18730294 # number of instructions that are conditional controls
system.cpu.num_int_insts 153161571 # number of integer instructions
2015-04-03 18:42:11 +02:00
system.cpu.num_fp_insts 11484 # number of float instructions
2016-08-02 12:34:32 +02:00
system.cpu.num_int_register_reads 285044694 # number of times the integer registers were read
2016-07-21 18:19:18 +02:00
system.cpu.num_int_register_writes 107178579 # number of times the integer registers were written
2015-04-03 18:42:11 +02:00
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
2016-07-21 18:19:18 +02:00
system.cpu.num_cc_register_reads 530850452 # number of times the CC registers were read
system.cpu.num_cc_register_writes 62364047 # number of times the CC registers were written
system.cpu.num_mem_refs 55938751 # number of memory refs
system.cpu.num_load_insts 31855653 # Number of load instructions
system.cpu.num_store_insts 24083098 # Number of store instructions
system.cpu.num_idle_cycles 5389630889.858858 # Number of idle cycles
system.cpu.num_busy_cycles 178082259.141142 # Number of busy cycles
2015-04-03 18:42:11 +02:00
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
2016-07-21 18:19:18 +02:00
system.cpu.Branches 36397005 # Number of branches fetched
2015-03-19 09:06:20 +01:00
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
2016-07-21 18:19:18 +02:00
system.cpu.op_class::IntAlu 121152199 68.36% 68.36% # Class of executed instruction
system.cpu.op_class::IntMult 116879 0.07% 68.43% # Class of executed instruction
2015-03-19 09:06:20 +01:00
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
2016-07-21 18:19:18 +02:00
system.cpu.op_class::MemRead 31855653 17.98% 86.41% # Class of executed instruction
system.cpu.op_class::MemWrite 24083098 13.59% 100.00% # Class of executed instruction
2015-03-19 09:06:20 +01:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-07-21 18:19:18 +02:00
system.cpu.op_class::total 177218735 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 819389 # number of replacements
2015-04-03 18:42:11 +02:00
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
2016-07-21 18:19:18 +02:00
system.cpu.dcache.tags.total_refs 53784005 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 819901 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.598170 # Average number of references to valid blocks.
2015-04-03 18:42:11 +02:00
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu.dcache.tags.tag_accesses 219235605 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 219235605 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 30128867 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 30128867 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22339858 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22339858 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits
2016-02-10 10:08:27 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
2016-07-21 18:19:18 +02:00
system.cpu.dcache.demand_hits::cpu.data 52468725 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 52468725 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 52863792 # number of overall hits
system.cpu.dcache.overall_hits::total 52863792 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 396279 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 396279 # number of ReadReq misses
2016-02-10 10:08:27 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
2015-04-03 18:42:11 +02:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.demand_misses::cpu.data 697942 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 697942 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 814061 # number of overall misses
system.cpu.dcache.overall_misses::total 814061 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 30525146 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 30525146 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22641521 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22641521 # number of WriteReq accesses(hits+misses)
2016-02-10 10:08:27 +01:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
2016-07-21 18:19:18 +02:00
system.cpu.dcache.demand_accesses::cpu.data 53166667 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 53166667 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 53677853 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 53677853 # number of overall (read+write) accesses
2015-04-03 18:42:11 +02:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
2016-02-10 10:08:27 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227156 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227156 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018483 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018483 # miss rate for LoadLockedReq accesses
2015-04-03 18:42:11 +02:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.013127 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.013127 # miss rate for demand accesses
2015-04-03 18:42:11 +02:00
system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-02-10 10:08:27 +01:00
system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
system.cpu.dcache.writebacks::total 682017 # number of writebacks
2016-07-21 18:19:18 +02:00
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1698989 # number of replacements
2016-02-10 10:08:27 +01:00
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
2016-07-21 18:19:18 +02:00
system.cpu.icache.tags.total_refs 145342052 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1699501 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 85.520427 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit.
2016-02-10 10:08:27 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
2015-04-03 18:42:11 +02:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu.icache.tags.tag_accesses 148741066 # Number of tag accesses
system.cpu.icache.tags.data_accesses 148741066 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 145342052 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 145342052 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 145342052 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 145342052 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 145342052 # number of overall hits
system.cpu.icache.overall_hits::total 145342052 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1699507 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1699507 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1699507 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1699507 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1699507 # number of overall misses
system.cpu.icache.overall_misses::total 1699507 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 147041559 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 147041559 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 147041559 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 147041559 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 147041559 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 147041559 # number of overall (read+write) accesses
2016-02-10 10:08:27 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
2015-04-03 18:42:11 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu.icache.writebacks::writebacks 1698989 # number of writebacks
system.cpu.icache.writebacks::total 1698989 # number of writebacks
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 109914 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65155.312641 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4524828 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 175195 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 25.827381 # Average number of references to valid blocks.
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 48764.064013 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931994 # Average occupied blocks per requestor
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.693007 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.619283 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.tags.tag_accesses 40578737 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40578737 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.WritebackClean_hits::writebacks 1666988 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1666988 # number of WritebackClean hits
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 151130 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 151130 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681192 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1681192 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505442 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 505442 # number of ReadSharedReq hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 1681192 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 656572 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2348982 # number of demand (read+write) hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_hits::cpu.inst 1681192 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 656572 # number of overall hits
system.cpu.l2cache.overall_hits::total 2348982 # number of overall hits
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 147777 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 147777 # number of ReadExReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.demand_misses::cpu.data 163345 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 181652 # number of demand (read+write) misses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_misses::cpu.data 163345 # number of overall misses
system.cpu.l2cache.overall_misses::total 181652 # number of overall misses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses)
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 1666988 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1666988 # number of WritebackClean accesses(hits+misses)
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699490 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1699490 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521010 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 521010 # number of ReadSharedReq accesses(hits+misses)
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 1699490 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 819917 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2530634 # number of demand (read+write) accesses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_accesses::cpu.inst 1699490 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 819917 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2530634 # number of overall (read+write) accesses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494391 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494391 # miss rate for ReadExReq accesses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199221 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.071781 # miss rate for demand accesses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199221 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.071781 # miss rate for overall accesses
2015-04-03 18:42:11 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
system.cpu.l2cache.writebacks::total 101950 # number of writebacks
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 5059879 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540474 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39263 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 2288317 # Transaction distribution
2015-04-03 18:42:11 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.trans_dist::WritebackClean 1698989 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 137372 # Transaction distribution
2015-04-03 18:42:11 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699507 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521010 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116047 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581961 # Packet count per connected master and slave (bytes)
2015-03-19 09:06:20 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.pkt_count::total 7753434 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306529 # Cumulative packet size per connected master and slave (bytes)
2015-03-19 09:06:20 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.pkt_size::total 313957213 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 182976 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 8840960 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 5318714 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.018479 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.134677 # Request fanout histogram
2015-03-19 09:06:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.snoop_fanout::0 5220428 98.15% 98.15% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 98286 1.85% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2015-03-19 09:06:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.snoop_fanout::total 5318714 # Request fanout histogram
system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-04-03 18:42:11 +02:00
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59002 # Transaction distribution
2015-03-19 09:06:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2015-03-19 09:06:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2015-03-19 09:06:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-04-03 18:42:11 +02:00
system.iocache.tags.replacements 36430 # number of replacements
2016-07-21 18:19:18 +02:00
system.iocache.tags.tagsinuse 0.909892 # Cycle average of tags in use
2015-04-03 18:42:11 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-07-21 18:19:18 +02:00
system.iocache.tags.warmup_cycle 227410175509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 0.909892 # Average occupied blocks per requestor
2016-02-10 10:08:27 +01:00
system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
2015-04-03 18:42:11 +02:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
system.iocache.tags.data_accesses 328176 # Number of data accesses
2016-07-21 18:19:18 +02:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-03-19 09:06:20 +01:00
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses
system.iocache.demand_misses::total 36464 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36464 # number of overall misses
system.iocache.overall_misses::total 36464 # number of overall misses
2015-04-03 18:42:11 +02:00
system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses
2015-04-03 18:42:11 +02:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2015-04-03 18:42:11 +02:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2015-03-19 09:06:20 +01:00
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-04-03 18:42:11 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2015-03-19 09:06:20 +01:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
2016-07-21 18:19:18 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
2015-04-03 18:42:11 +02:00
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::CleanEvict 8204 # Transaction distribution
2015-04-03 18:42:11 +02:00
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::ReadExReq 145998 # Transaction distribution
system.membus.trans_dist::ReadExResp 145998 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
2015-03-19 09:06:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506584 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613944 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_count::total 723302 # Packet count per connected master and slave (bytes)
2015-03-19 09:06:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092540 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255513 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_size::total 20587033 # Cumulative packet size per connected master and slave (bytes)
2015-04-03 18:42:11 +02:00
system.membus.snoops 0 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 434823 # Request fanout histogram
2015-03-19 09:06:20 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.membus.snoop_fanout::1 434823 100.00% 100.00% # Request fanout histogram
2015-03-19 09:06:20 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.membus.snoop_fanout::total 434823 # Request fanout histogram
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-03-19 09:06:20 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2015-04-03 18:42:11 +02:00
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
2015-03-19 09:06:20 +01:00
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
2015-04-03 18:42:11 +02:00
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
2015-03-19 09:06:20 +01:00
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
2015-04-03 18:42:11 +02:00
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
2015-03-19 09:06:20 +01:00
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
2015-04-03 18:42:11 +02:00
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-07-21 18:19:18 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
2015-03-19 09:06:20 +01:00
---------- End Simulation Statistics ----------