2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2012-02-13 19:30:30 +01:00
|
|
|
sim_seconds 0.464073 # Number of seconds simulated
|
|
|
|
|
sim_ticks 464073050000 # Number of ticks simulated
|
|
|
|
|
final_tick 464073050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2011-01-18 23:30:06 +01:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2012-02-13 19:30:30 +01:00
|
|
|
host_inst_rate 176271 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_op_rate 196643 # Simulator op (including micro ops) rate (op/s)
|
|
|
|
|
host_tick_rate 52961695 # Simulator tick rate (ticks/s)
|
|
|
|
|
host_mem_usage 223676 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 8762.43 # Real time elapsed on the host
|
|
|
|
|
sim_insts 1544563056 # Number of instructions simulated
|
|
|
|
|
sim_ops 1723073869 # Number of ops (including micro ops) simulated
|
|
|
|
|
system.physmem.bytes_read 189754368 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read 48448 # Number of instructions bytes read from this memory
|
|
|
|
|
system.physmem.bytes_written 78230272 # Number of bytes written to this memory
|
|
|
|
|
system.physmem.num_reads 2964912 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_writes 1222348 # Number of write requests responded to by this memory
|
2012-01-25 18:19:50 +01:00
|
|
|
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
2012-02-13 19:30:30 +01:00
|
|
|
system.physmem.bw_read 408889006 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read 104397 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_write 168573185 # Write bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total 577462190 # Total bandwidth to/from this memory (bytes/s)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 46 # Number of system calls
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.numCycles 928146101 # number of cpu cycles simulated
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.BPredUnit.lookups 300566019 # Number of BP lookups
|
|
|
|
|
system.cpu.BPredUnit.condPredicted 246342426 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.BPredUnit.condIncorrect 16106991 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.BPredUnit.BTBLookups 172736235 # Number of BTB lookups
|
|
|
|
|
system.cpu.BPredUnit.BTBHits 156347078 # Number of BTB hits
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.BPredUnit.usedRAS 18335765 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.BPredUnit.RASInCorrect 410 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 292802110 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 2158556881 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 300566019 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 174682843 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 429264774 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 83785432 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.BlockedCycles 129176492 # Number of cycles fetch has spent blocked
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.PendingTrapStallCycles 309 # Number of stall cycles due to pending traps
|
|
|
|
|
system.cpu.fetch.CacheLines 283792946 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 5380579 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 918501449 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.613879 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.238743 # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.fetch.rateDist::0 489236723 53.26% 53.26% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 23024875 2.51% 55.77% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 38786234 4.22% 59.99% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 47824320 5.21% 65.20% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 40756189 4.44% 69.64% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 46964078 5.11% 74.75% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 39095628 4.26% 79.01% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 18144974 1.98% 80.98% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 174668428 19.02% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.fetch.rateDist::total 918501449 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.323835 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 2.325665 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 322112975 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 109206216 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 403275742 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 16649458 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 67257058 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 46176709 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 759 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 2347040926 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 2511 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 67257058 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 343744693 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 50775772 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 22198 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 397120131 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 59581597 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 2290149919 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 23251 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 4667919 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LSQFullEvents 46275027 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
|
|
|
|
|
system.cpu.rename.RenamedOperands 2264746735 # Number of destination operands rename has renamed
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.rename.RenameLookups 10570831764 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 10570827058 # Number of integer rename lookups
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.rename.fp_rename_lookups 4706 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.CommittedMaps 1706319983 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.UndoneMaps 558426752 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 136911238 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 624866711 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 218769389 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 86004799 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 66542105 # Number of conflicting stores.
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iq.iqInstsAdded 2190647853 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 1858 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 2016093743 # Number of instructions issued
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.iqSquashedInstsIssued 4890618 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 462875235 # Number of squashed instructions iterated over during squash; mainly for profiling
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 1075025863 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1351 # Number of squashed non-spec instructions that were removed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::samples 918501449 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 2.194982 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.923350 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::0 251234212 27.35% 27.35% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 138874484 15.12% 42.47% # Number of insts issued each cycle
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::2 158306174 17.24% 59.71% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 116338080 12.67% 72.37% # Number of insts issued each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::4 125703968 13.69% 86.06% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 75541719 8.22% 94.28% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 39131512 4.26% 98.54% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 10691268 1.16% 99.71% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 2680032 0.29% 100.00% # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 918501449 # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.fu_full::IntAlu 823704 3.29% 3.29% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 4653 0.02% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 18995164 75.78% 79.08% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 5243478 20.92% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 1234318256 61.22% 61.22% # Type of FU issued
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntMult 931291 0.05% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 86 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 19 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 587032832 29.12% 90.39% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 193811220 9.61% 100.00% # Type of FU issued
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 2016093743 # Type of FU issued
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.rate 2.172173 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 25066999 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst)
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iq.int_inst_queue_reads 4980646048 # Number of integer instruction queue reads
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.int_inst_queue_writes 2653710289 # Number of integer instruction queue writes
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1958144551 # Number of integer instruction queue wakeup accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 870 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 197 # Number of floating instruction queue wakeup accesses
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iq.int_alu_accesses 2041160487 # Number of integer alu accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.fp_alu_accesses 255 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 63652463 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 138939936 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 281971 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 189096 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 43922339 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 450534 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 67257058 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 23170910 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1317099 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2190657684 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 5590225 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 624866711 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 218769389 # Number of dispatched store instructions
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1791 # Number of dispatched non-speculative instructions
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.iewIQFullEvents 207758 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 50528 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 189096 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 8640354 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 10202609 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 18842963 # Number of branch mispredicts detected at execute
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iew.iewExecutedInsts 1986590915 # Number of executed instructions
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.iewExecLoadInsts 572448085 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 29502828 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.exec_nop 7973 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 763288309 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 238204396 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 190840224 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.140386 # Inst execution rate
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iew.wb_sent 1967133109 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1958144748 # cumulative count of insts written-back
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.wb_producers 1296172102 # num instructions producing a value
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.iew.wb_consumers 2068722658 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.wb_rate 2.109738 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.626557 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 1544563074 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitCommittedOps 1723073887 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 467651163 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 507 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.branchMispredicts 16106465 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 851244392 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.024182 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.756273 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 363008407 42.64% 42.64% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 192701589 22.64% 65.28% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 73550522 8.64% 73.92% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 35106838 4.12% 78.05% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 18707332 2.20% 80.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 30658705 3.60% 83.85% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 19651115 2.31% 86.15% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 10957875 1.29% 87.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 106902009 12.56% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 851244392 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committedInsts 1544563074 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 1723073887 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.refs 660773825 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 485926775 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.branches 213462369 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.int_insts 1536941869 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.bw_lim_events 106902009 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.rob.rob_reads 2935066834 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4448881416 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 899412 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 9644652 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 1544563056 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 1723073869 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1544563056 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.600912 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.600912 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.664138 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.664138 # IPC: Total IPC of All Threads
|
2012-03-06 17:14:54 +01:00
|
|
|
system.cpu.int_regfile_reads 9951907734 # number of integer regfile reads
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.int_regfile_writes 1938294940 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 210 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 230 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 2898206993 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 134 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 22 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 634.912102 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 283791788 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 361058.254453 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 634.912102 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.310016 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.310016 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 283791788 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 283791788 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 283791788 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 283791788 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 283791788 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 283791788 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 1158 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 38624000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 38624000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 38624000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 38624000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 38624000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 38624000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 283792946 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 283792946 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 283792946 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 283792946 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 283792946 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 283792946 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33354.058722 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 372 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 372 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 372 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 372 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 372 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27049500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 27049500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27049500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 27049500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27049500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 27049500 # number of overall MSHR miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34414.122137 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.replacements 9618384 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4087.732309 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 660741585 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 9622480 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 68.666454 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 3347848000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4087.732309 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.997982 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.997982 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 493363105 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 493363105 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 167378321 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 167378321 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 93 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 93 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 66 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 66 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 660741426 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 660741426 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 660741426 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 660741426 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 10695472 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 10695472 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5207726 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 5207726 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 15903198 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 15903198 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 15903198 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 15903198 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 189107739500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 189107739500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 129597679387 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 129597679387 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 148000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 148000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 318705418887 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 318705418887 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 318705418887 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 318705418887 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 504058577 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 504058577 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 66 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 66 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 676644624 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 676644624 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 676644624 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 676644624 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021219 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041237 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.023503 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.023503 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.102760 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24885.656309 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 270494777 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 161000 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 91798 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.630395 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 16100 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 3133951 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 3133951 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2966989 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2966989 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313729 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3313729 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 6280718 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 6280718 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 6280718 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 6280718 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7728483 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7728483 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893997 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1893997 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9622480 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 9622480 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9622480 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 9622480 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93034311000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 93034311000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45389589120 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 45389589120 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138423900120 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 138423900120 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138423900120 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 138423900120 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015333 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12037.848954 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23964.974137 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14385.470286 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14385.470286 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.replacements 2952443 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 26872.767236 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 7878289 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 2979766 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 2.643929 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 101003264500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 10760.518963 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 11.047760 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 16101.200513 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.328385 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.000337 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.491370 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.820092 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 5679969 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 5679997 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3133951 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 3133951 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 978347 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 978347 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 6658316 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 6658344 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 6658316 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 6658344 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 758 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 2048513 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 2049271 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 915651 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 915651 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 758 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 2964164 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 2964922 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 758 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 2964164 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 2964922 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26043500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70322097500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 70348141000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31765624000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 31765624000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 26043500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 102087721500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 102113765000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 26043500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 102087721500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 102113765000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 786 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7728482 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 7729268 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3133951 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 3133951 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893998 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1893998 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 786 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9622480 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 9623266 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 786 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9622480 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 9623266 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964377 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265060 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483449 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964377 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.308046 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964377 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.308046 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.179420 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.362817 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34691.846566 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.179420 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.645491 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.179420 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.645491 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 57298000 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 6751 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8487.335210 # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 1222348 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 1222348 # number of writebacks
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2048504 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 2049261 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915651 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 915651 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2964155 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 2964912 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2964155 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 2964912 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23603500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63886529000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63910132500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922104500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922104500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23603500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92808633500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 92832237000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23603500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92808633500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 92832237000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265059 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483449 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31180.317041 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.919332 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.384441 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
