gem5/src/cpu/o3
2011-02-23 15:10:50 -06:00
..
base_dyn_inst.cc O3CPU: Make the instcount debugging stuff per-cpu. 2008-11-10 11:51:18 -08:00
bpred_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
bpred_unit_impl.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
checker_builder.cc CPU: Make the cpuid parameter get set in SE mode as well. 2007-10-02 18:33:57 -07:00
comm.hh O3: Fix mispredicts from non control instructions. 2011-01-18 16:30:05 -06:00
commit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
commit.hh mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
commit_impl.hh ARM: Do something for ISB, DSB, DMB 2011-02-23 15:10:49 -06:00
cpu.cc mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
cpu.hh mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
cpu_builder.cc o3-smt: enforce numThreads parameter for SMT SE mode 2009-07-25 00:50:27 -04:00
cpu_policy.hh gcc: Version 4.3 is pretty anal about shadowing types, placate it. 2008-09-22 08:25:57 -07:00
decode.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
decode.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
decode_impl.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
dep_graph.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
dyn_inst.cc O3: Generaize the O3 IMPL class so it isn't split out by ISA. 2008-10-09 00:10:02 -07:00
dyn_inst.hh ARM: Add support for moving predicated false dest operands from sources. 2011-01-18 16:30:02 -06:00
dyn_inst_impl.hh O3: Make all instructions that write a misc. register not perform the write until commit. 2010-12-07 16:19:57 -08:00
fetch.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
fetch.hh O3: Fix bug when a squash occurs right before TLB miss returns. 2011-02-23 15:10:49 -06:00
fetch_impl.hh O3: Fix bug when a squash occurs right before TLB miss returns. 2011-02-23 15:10:49 -06:00
free_list.cc types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
free_list.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
fu_pool.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
fu_pool.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
FuncUnitConfig.py CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
FUPool.py CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
iew.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
iew.hh Move sched_list.hh and timebuf.hh from src/base to src/cpu. 2011-01-03 14:35:47 -08:00
iew_impl.hh O3: When a prefetch causes a fault, don't record it in the inst 2011-02-23 15:10:50 -06:00
impl.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
inst_queue.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
inst_queue.hh O3: Enhance data address translation by supporting hardware page table walkers. 2011-02-11 18:29:35 -06:00
inst_queue_impl.hh O3: If there is an outstanding table walk don't let the inst queue sleep. 2011-02-23 15:10:49 -06:00
isa_specific.hh O3: Generaize the O3 IMPL class so it isn't split out by ISA. 2008-10-09 00:10:02 -07:00
lsq.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq.hh CPU: Add readBytes and writeBytes functions to the exec contexts. 2010-08-13 06:16:02 -07:00
lsq_impl.hh Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
lsq_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq_unit.hh Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
lsq_unit_impl.hh O3: Enhance data address translation by supporting hardware page table walkers. 2011-02-11 18:29:35 -06:00
mem_dep_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
mem_dep_unit.hh types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
mem_dep_unit_impl.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
O3Checker.py python: Move more code into m5.util allow SCons to use that code. 2009-09-22 15:24:16 -07:00
O3CPU.py Config: Keep track of uncached and cached ports separately. 2011-02-03 20:23:00 -08:00
regfile.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
rename.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rename.hh mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
rename_impl.hh mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
rename_map.cc Make the floating point zero register special handling only apply for ALPHA. 2007-04-22 17:50:43 +00:00
rename_map.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
rob.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rob.hh mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
rob_impl.hh mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
sat_counter.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
sat_counter.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
SConscript inorder-o3: allow both to compile together 2009-05-12 15:01:14 -04:00
SConsopts cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
scoreboard.cc Alpha: Fix Alpha NumMiscArchRegs constant. 2010-10-04 11:58:06 -07:00
scoreboard.hh Alpha: Fix Alpha NumMiscArchRegs constant. 2010-10-04 11:58:06 -07:00
store_set.cc types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
store_set.hh types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
thread_context.cc O3: Generaize the O3 IMPL class so it isn't split out by ISA. 2008-10-09 00:10:02 -07:00
thread_context.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
thread_context_impl.hh Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
thread_state.hh Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00