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gem5/cpu
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Kevin Lim 759ff4b910 Updates for OzoneCPU. 
build/SConstruct:
    Include Ozone CPU models.
cpu/cpu_models.py:
    Include OzoneCPU models.

--HG--
extra : convert_revision : 51a016c216cacd2cc613eed79653026c2edda4b3
2006-04-22 18:45:01 -04:00
..
memtest Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
o3 Updates for O3 model. 2006-04-22 18:26:48 -04:00
ozone Updates for OzoneCPU. 2006-04-22 18:45:01 -04:00
simple Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 2006-03-09 15:15:55 -05:00
trace Made Addr a global type 2006-02-21 03:38:21 -05:00
base.cc Fixes to allow the ExecContext to be used for profiling. 2006-03-07 22:21:39 -05:00
base.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
base_dyn_inst.cc Updates for O3 model. 2006-04-22 18:26:48 -04:00
base_dyn_inst.hh Updates for O3 model. 2006-04-22 18:26:48 -04:00
cpu_exec_context.cc Move quiesce event to its own class. 2006-04-22 18:11:54 -04:00
cpu_exec_context.hh Move quiesce event to its own class. 2006-04-22 18:11:54 -04:00
cpu_models.py Updates for OzoneCPU. 2006-04-22 18:45:01 -04:00
exec_context.hh no more common syscall emulation, now common for everyone 2006-03-09 15:42:09 -05:00
exetrace.cc Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
exetrace.hh Made Addr a global type 2006-02-21 03:38:21 -05:00
inst_seq.hh fix problems on darwin/*BSD for syscall emulation mode 2006-02-10 14:21:32 -05:00
intr_control.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
intr_control.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
pc_event.cc Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
pc_event.hh Made Addr a global type 2006-02-21 03:38:21 -05:00
profile.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
profile.hh Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
quiesce_event.cc Move quiesce event to its own class. 2006-04-22 18:11:54 -04:00
quiesce_event.hh Move quiesce event to its own class. 2006-04-22 18:11:54 -04:00
SConscript Updates for O3 model. 2006-04-22 18:26:48 -04:00
smt.hh Many files: 2005-06-05 05:16:00 -04:00
static_inst.cc Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. 2006-02-19 02:34:37 -05:00
static_inst.hh Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included. 2006-03-03 15:28:25 -05:00
thread_state.hh Updates for O3 model. 2006-04-22 18:26:48 -04:00