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cache
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MEM: Make CLREX a first class request operation and clear locks in caches when it in received
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2010-08-23 11:18:41 -05:00 |
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config
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Fixes to get prefetching working again.
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2009-02-16 08:56:40 -08:00 |
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protocol
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MOESI_hammer: fixed bug for dma reads in single cpu systems
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2010-08-24 12:06:53 -07:00 |
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ruby
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testers: move testers to a new directory
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2010-08-24 12:07:22 -07:00 |
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slicc
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ruby: Stall and wait input messages instead of recycling
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2010-08-20 11:46:14 -07:00 |
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bridge.cc
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ruby: Added more info to bridge error message
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2009-11-18 13:55:57 -08:00 |
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bridge.hh
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includes: use base/types.hh not inttypes.h or stdint.h
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2009-05-17 14:34:51 -07:00 |
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Bridge.py
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DMA: Add IOCache and fix bus bridge to optionally only send requests one
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2007-08-10 16:14:01 -04:00 |
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bus.cc
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bus: clean up default responder code.
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2010-08-17 05:06:21 -07:00 |
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bus.hh
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bus: clean up default responder code.
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2010-08-17 05:06:21 -07:00 |
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Bus.py
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bus: clean up default responder code.
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2010-08-17 05:06:21 -07:00 |
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dram.cc
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style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
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2008-09-10 14:26:15 -04:00 |
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dram.hh
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stats: Fix all stats usages to deal with template fixes
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2009-03-05 19:09:53 -08:00 |
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mem_object.cc
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params: Get rid of the remnants of the old style parameter configuration stuff.
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2008-08-11 12:22:17 -07:00 |
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mem_object.hh
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params: Get rid of the remnants of the old style parameter configuration stuff.
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2008-08-11 12:22:17 -07:00 |
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MemObject.py
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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mport.cc
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X86: Add a function which gets called when an interrupt message has been delivered.
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2009-04-19 03:54:11 -07:00 |
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mport.hh
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Create a message port for sending messages as apposed to reading/writing a memory range.
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2008-10-12 12:08:51 -07:00 |
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packet.cc
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cache: fail store conditionals when upgrade loses race
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2010-06-16 15:25:57 -07:00 |
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packet.hh
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ruby: fix ruby llsc support to sync sc outcomes
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2010-08-20 11:46:12 -07:00 |
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packet_access.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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page_table.cc
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util: do checkpoint aggregation more cleanly, fix last changeset.
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2010-01-19 22:03:44 -08:00 |
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page_table.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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physical.cc
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util: do checkpoint aggregation more cleanly, fix last changeset.
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2010-01-19 22:03:44 -08:00 |
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physical.hh
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types: clean up types, especially signed vs unsigned
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2009-06-04 23:21:12 -07:00 |
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PhysicalMemory.py
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Make default PhysicalMemory latency slightly more realistic.
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2008-08-03 18:13:29 -04:00 |
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port.cc
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types: clean up types, especially signed vs unsigned
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2009-06-04 23:21:12 -07:00 |
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port.hh
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types: clean up types, especially signed vs unsigned
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2009-06-04 23:21:12 -07:00 |
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port_impl.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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request.hh
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MEM: Make CLREX a first class request operation and clear locks in caches when it in received
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2010-08-23 11:18:41 -05:00 |
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SConscript
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ruby: Convert most Ruby objects to M5 SimObjects.
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2010-01-29 20:29:17 -08:00 |
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tport.cc
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Port: Only indicate that a SimpleTimingPort is drained if its send event is
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2010-07-22 18:54:37 +01:00 |
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tport.hh
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Clean up the SimpleTimingPort class a little bit.
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2008-11-10 11:51:18 -08:00 |
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translating_port.cc
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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translating_port.hh
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fix the translating ports so it can add a page on a fault
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2007-05-09 15:37:46 -04:00 |
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vport.cc
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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vport.hh
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
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