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gem5/src/cpu/o3
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Kevin Lim e1054170b5 o3: Fix for retry ID bug. 
It should be cleared prior to the call to recvRetry.
Add extra DPRINTF statement for clearer debugging output.

--HG--
extra : convert_revision : e2332754743f42d60e159ac89f6fb0fd8b7f57f8
2007-08-21 16:16:56 -07:00
..
alpha Fix problem with tracer not being initialized. 2007-07-30 13:13:11 -07:00
mips Fix problem with tracer not being initialized. 2007-07-30 13:13:11 -07:00
sparc Fix problem with tracer not being initialized. 2007-07-30 13:13:11 -07:00
2bit_local_pred.cc Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 2006-06-04 16:07:54 -04:00
2bit_local_pred.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
base_dyn_inst.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
bpred_unit_impl.hh Make sure the value of PC is actually updated now that the instruction target isn't set explicitly. 2006-12-28 14:29:17 -05:00
btb.cc Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
btb.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
checker_builder.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
comm.hh Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. 2007-04-14 17:13:18 +00:00
commit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
commit.hh Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. 2007-04-14 17:13:18 +00:00
commit_impl.hh Event descriptions should not end in "event" 2007-06-30 17:45:58 -07:00
cpu.cc Merge python and x86 changes with cache branch 2007-07-26 23:15:49 -07:00
cpu.hh Merge zizzer.eecs.umich.edu:/bk/newmem 2007-06-21 20:35:25 +00:00
cpu_policy.hh Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 2006-06-04 16:07:54 -04:00
decode.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
decode.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
decode_impl.hh Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. 2007-04-14 17:13:18 +00:00
dep_graph.hh Miscellaneous minor fixes. 2006-06-16 17:15:18 -04:00
dyn_inst.hh Added an x86 dyninst 2007-03-05 14:55:45 +00:00
fetch.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
fetch.hh Merge zizzer.eecs.umich.edu:/bk/newmem 2007-06-19 18:54:40 -07:00
fetch_impl.hh Merge Gabe's changes from head. 2007-07-29 13:25:14 -07:00
free_list.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
free_list.hh Make the floating point zero register special handling only apply for ALPHA. 2007-04-22 17:50:43 +00:00
fu_pool.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
fu_pool.hh Update copyright. 2006-06-07 16:02:55 -04:00
FuncUnitConfig.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
FUPool.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
iew.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
iew.hh Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect. 2007-04-13 13:59:31 +00:00
iew_impl.hh Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. 2007-04-14 17:13:18 +00:00
inst_queue.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
inst_queue.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
inst_queue_impl.hh Merge python and x86 changes with cache branch 2007-07-26 23:15:49 -07:00
isa_specific.hh Initial changes to get O3 working with SPARC 2006-11-24 22:06:33 -05:00
lsq.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq.hh Change getDeviceAddressRanges to use bool for snoop arg. 2007-05-21 23:36:09 -07:00
lsq_impl.hh o3: Fix for retry ID bug. 2007-08-21 16:16:56 -07:00
lsq_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq_unit.hh Make CPU models use new LoadLockedReq/StoreCondReq commands. 2007-06-30 20:35:42 -07:00
lsq_unit_impl.hh o3: Fix for retry ID bug. 2007-08-21 16:16:56 -07:00
mem_dep_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
mem_dep_unit.hh Initialize mem dep unit properly. 2006-11-07 13:53:06 -05:00
mem_dep_unit_impl.hh Handle status bits a little better, as well as non-speculative instructions. 2007-03-23 11:40:53 -04:00
O3Checker.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
O3CPU.py Make sure all parameters have default values if they're 2007-06-20 08:14:11 -07:00
params.hh Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. 2006-10-31 14:33:56 -05:00
ras.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
ras.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
regfile.hh Make the floating point zero register special handling only apply for ALPHA. 2007-04-22 17:50:43 +00:00
rename.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rename.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
rename_impl.hh Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. 2007-04-14 17:13:18 +00:00
rename_map.cc Make the floating point zero register special handling only apply for ALPHA. 2007-04-22 17:50:43 +00:00
rename_map.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
rob.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rob.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
rob_impl.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
sat_counter.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
sat_counter.hh Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
SConscript Fix cut-n-pasto to make the path correct 2007-05-30 17:19:20 -07:00
SConsopts Rework the way SCons recurses into subdirectories, making it 2007-03-10 23:00:54 -08:00
scoreboard.cc Make the floating point zero register special handling only apply for ALPHA. 2007-04-22 17:50:43 +00:00
scoreboard.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
store_set.cc Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses. 2006-06-05 18:14:39 -04:00
store_set.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
thread_context.hh *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 2007-03-07 15:04:31 -05:00
thread_context_impl.hh fix segfault when peer owner attempts to use functional port 2007-03-13 17:34:52 -04:00
thread_state.hh Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. 2006-10-31 14:33:56 -05:00
tournament_pred.cc Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
tournament_pred.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00