Andreas Hansson df8df4fd0a stats: Bump stats for decoder, TLB, prefetcher and DRAM changes ... Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.		2014-12-23 09:31:20 -05:00
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config.ini	stats: updates due to changes to ruby	2014-11-06 05:42:21 -06:00
simerr	stats: update stats for cache occupancy and clock domain changes	2014-01-24 15:29:33 -06:00
simout	stats: update stats for cache occupancy and clock domain changes	2014-01-24 15:29:33 -06:00
stats.txt	stats: Bump stats for decoder, TLB, prefetcher and DRAM changes	2014-12-23 09:31:20 -05:00