gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer
Andreas Hansson df8df4fd0a stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
2014-12-23 09:31:20 -05:00
..
config.ini stats: updates due to changes to ruby 2014-11-06 05:42:21 -06:00
simerr stats: updates due to recent ruby and x86 changes 2014-09-01 16:55:52 -05:00
simout stats: update stats for cache occupancy and clock domain changes 2014-01-24 15:29:33 -06:00
stats.txt stats: Bump stats for decoder, TLB, prefetcher and DRAM changes 2014-12-23 09:31:20 -05:00