gem5/src/arch
Michael LeBeane dc16c1ceb8 dev: Add m5 op to toggle synchronization for dist-gem5.
This patch adds the ability for an application to request dist-gem5 to begin/
end synchronization using an m5 op. When toggling on sync, all nodes agree
on the next sync point based on the maximum of all nodes' ticks. CPUs are
suspended until the sync point to avoid sending network messages until sync has
been enabled. Toggling off sync acts like a global execution barrier, where
all CPUs are disabled until every node reaches the toggle off point. This
avoids tricky situations such as one node hitting a toggle off followed by a
toggle on before the other nodes hit the first toggle off.
2016-10-26 22:48:40 -04:00
..
alpha isa: Modify get/check interrupt routines 2016-07-21 17:19:15 +01:00
arm cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass 2016-10-15 14:58:45 -05:00
generic cpu, arch: fix the type used for the request flags 2016-08-15 12:00:35 +01:00
hsail gpu-compute: support in-order data delivery in GM pipe 2016-10-26 22:48:28 -04:00
mips isa: Modify get/check interrupt routines 2016-07-21 17:19:15 +01:00
null cpu,isa,mem: Add per-thread wakeup logic 2015-09-30 11:14:19 -05:00
power isa: Modify get/check interrupt routines 2016-07-21 17:19:15 +01:00
sparc isa: Modify get/check interrupt routines 2016-07-21 17:19:15 +01:00
x86 dev: Add m5 op to toggle synchronization for dist-gem5. 2016-10-26 22:48:40 -04:00
isa_parser.py cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass 2016-10-15 14:58:45 -05:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF 2016-10-26 22:47:38 -04:00