gem5/src/arch/sparc
2009-01-30 20:04:17 -05:00
..
isa mem: update stuff for changes to Packet and Request 2008-11-10 11:51:17 -08:00
linux syscalls: fix latent brk/obreak bug. 2008-11-15 09:30:10 -08:00
solaris syscalls: fix latent brk/obreak bug. 2008-11-15 09:30:10 -08:00
asi.cc Panic if any CMT registers are accessed 2007-03-08 21:49:13 -05:00
asi.hh Panic if any CMT registers are accessed 2007-03-08 21:49:13 -05:00
faults.cc gcc: Add extra parens to quell warnings. 2008-09-27 21:03:49 -07:00
faults.hh Address translation: Make the page table more flexible. 2007-08-26 20:33:57 -07:00
floatregfile.cc fix mostly floating point related 2007-02-02 18:04:42 -05:00
floatregfile.hh Moved some constants from isa_traits.hh to the reg file headers. 2006-11-22 23:49:44 -05:00
handlers.hh SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault ASI accesses work. 2007-08-13 16:02:47 -07:00
interrupts.cc Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
interrupts.hh CPU: Add a setCPU function to the interrupt objects. 2009-01-25 20:29:03 -08:00
intregfile.cc Make SPARC checkpointing work 2007-01-30 18:25:39 -05:00
intregfile.hh Fixed an off-by-one error. 2007-03-08 00:55:16 -05:00
isa_traits.hh style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
kernel_stats.hh Put kernel_stats back into arch. 2006-11-07 22:34:34 -05:00
locked_mem.hh Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) 2006-10-08 10:53:24 -07:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
miscregfile.cc style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
miscregfile.hh eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
mmaped_ipr.hh reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes) 2006-12-04 19:39:57 -05:00
pagetable.cc Make SPARC checkpointing work 2007-01-30 18:25:39 -05:00
pagetable.hh misc: remove #include <cassert> from misc.hh since not everyone needs it. 2008-10-10 10:15:00 -07:00
predecoder.hh Predecoder: Clear out predecoder state on an ITLB fault. 2007-10-02 22:21:38 -07:00
process.cc imported patch aux-fix.patch 2008-12-07 15:07:42 -05:00
process.hh This patch pulls out the auxiliary vector struct from individual ISA 2008-12-04 18:03:35 -05:00
regfile.cc Get rid of old RegContext code. 2008-10-12 17:57:46 -07:00
regfile.hh Get rid of old RegContext code. 2008-10-12 17:57:46 -07:00
remote_gdb.cc arch: TheISA shouldn't really ever be used in the arch directory. 2008-09-27 21:03:46 -07:00
remote_gdb.hh SPARC,Remote GDB: Fix an accounting bug in the remote gdb stuff. 2007-10-02 18:24:24 -07:00
SConscript tracing: Add help strings for some of the trace flags 2009-01-19 09:59:14 -08:00
SConsopts Rework the way SCons recurses into subdirectories, making it 2007-03-10 23:00:54 -08:00
sparc_traits.hh style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
SparcInterrupts.py Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
SparcSystem.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
SparcTLB.py TLB: Make all tlbs derive from a common base class in both python and C++. 2008-10-10 23:47:42 -07:00
stacktrace.cc arch: TheISA shouldn't really ever be used in the arch directory. 2008-09-27 21:03:46 -07:00
stacktrace.hh arch: TheISA shouldn't really ever be used in the arch directory. 2008-09-27 21:03:46 -07:00
syscallreturn.hh SPARC: Truncate syscall args and return values appropriately. 2008-12-16 23:06:37 -08:00
system.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
system.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
tlb.cc Errors: Use the correct panic/warn/fatal/info message in some places. 2009-01-30 20:04:17 -05:00
tlb.hh sparc: Fix style, create a helper function for translation. 2008-09-23 20:38:02 -07:00
tlb_map.hh When nesting if statements, use braces to avoid ambiguous else clauses. 2008-09-26 08:18:57 -07:00
types.hh Get rid of old RegContext code. 2008-10-12 17:57:46 -07:00
ua2005.cc Fix a few more places where the context stuff wasn't changed 2008-11-05 07:20:03 -08:00
utility.cc Remove delVirtPort() and make getVirtPort() only return cached version. 2008-07-01 10:25:07 -04:00
utility.hh Arguments: Get rid of duplicate code for the Arguments class in each architecture. 2007-08-01 16:59:14 -04:00
vtophys.cc style: bring this file into M5 style, use the new pte translate function. 2008-09-26 08:18:55 -07:00
vtophys.hh implement vtophys and 32bit gdb support 2007-02-18 19:57:46 -05:00