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gem5/src/arch/sparc
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Rekai Gonzalez Alberquilla d3d159749a isa: Add parameter to pick different decoder inside ISA 
The decoder is responsible for splitting instructions in micro
operations (uops). Given that different micro architectures may split
operations differently, this patch allows to specify which micro
architecture each isa implements, so different cores in the system can
split instructions differently, also decoupling uop splitting
(microArch) from ISA (Arch). This is done making the decodification
calls templates that receive a type 'DecoderFlavour' that maps the
name of the operation to the class that implements it. This way there
is only one selection point (converting the command line enum to the
appropriate DecodeFeatures object). In addition, there is no explicit
code replication: template instantiation hides that, and the compiler
should be able to resolve a number of things at compile-time.
2015-10-09 14:50:54 -05:00
..
isa arch: Use shared_ptr for all Faults 2014-10-16 05:49:51 -04:00
linux sim: revert 6709bbcf564d 2014-10-22 15:59:57 -05:00
solaris MEM: Add port proxies instead of non-structural ports 2012-01-17 12:55:08 -06:00
asi.cc SPARC: Clean up some historical style issues. 2010-11-11 02:03:58 -08:00
asi.hh SPARC: Clean up some historical style issues. 2010-11-11 02:03:58 -08:00
decoder.cc ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
decoder.hh isa: Add parameter to pick different decoder inside ISA 2015-10-09 14:50:54 -05:00
faults.cc arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
faults.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
handlers.hh gcc: Fix warnings for gcc 4.7 and clang 3.1 2012-07-02 08:21:53 -04:00
interrupts.cc Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
interrupts.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
isa.cc isa,cpu: Add support for FS SMT Interrupts 2015-09-30 11:14:19 -05:00
isa.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
isa_traits.hh arch: Cleanup unused ISA traits constants 2014-09-03 07:42:21 -04:00
kernel_stats.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
locked_mem.hh cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped. 2014-01-24 15:29:30 -06:00
microcode_rom.hh SPARC: Clean up some historical style issues. 2010-11-11 02:03:58 -08:00
miscregs.hh sparc: Fixup bit ordering in the PSTATE bit union 2014-08-26 10:13:23 -04:00
mmapped_ipr.hh arch: Add support for m5ops using mmapped IPRs 2013-09-30 12:20:43 +02:00
mt.hh clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6 2012-04-14 05:43:31 -04:00
nativetrace.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
nativetrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
pagetable.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
pagetable.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
process.cc arch: Cleanup unused ISA traits constants 2014-09-03 07:42:21 -04:00
process.hh mem: adding architectural page table support for SE mode 2014-08-28 10:11:44 -05:00
pseudo_inst.hh kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00
registers.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
remote_gdb.cc misc: Generalize GDB single stepping. 2014-12-05 22:37:03 -08:00
remote_gdb.hh misc: Generalize GDB single stepping. 2014-12-05 22:37:03 -08:00
SConscript arch: teach ISA parser how to split code across files 2014-05-09 18:58:47 -04:00
SConsopts Rework the way SCons recurses into subdirectories, making it 2007-03-10 23:00:54 -08:00
sparc_traits.hh SPARC: Clean up some historical style issues. 2010-11-11 02:03:58 -08:00
SparcInterrupts.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
SparcISA.py arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
SparcNativeTrace.py cpu: Put all CPU instruction tracers in a single file 2015-01-25 07:22:17 -05:00
SparcSystem.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
SparcTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
stacktrace.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
system.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
system.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
tlb.cc isa,cpu: Add support for FS SMT Interrupts 2015-09-30 11:14:19 -05:00
tlb.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
tlb_map.hh clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6 2012-04-14 05:43:31 -04:00
types.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
ua2005.cc isa,cpu: Add support for FS SMT Interrupts 2015-09-30 11:14:19 -05:00
utility.cc revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
utility.hh arch: Use shared_ptr for all Faults 2014-10-16 05:49:51 -04:00
vtophys.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
vtophys.hh MEM: Clean-up of Functional/Virtual/TranslatingPort remnants 2012-01-30 03:44:25 -05:00