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probe
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base: add support for probe points and common probes
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2014-01-24 15:29:30 -06:00 |
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base_dyn_inst.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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checker.cc
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sim: Add the notion of clock domains to all ClockedObjects
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2013-06-27 05:49:49 -04:00 |
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checker.hh
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cpu: Add header files for checker CPUs
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2012-11-02 11:32:01 -05:00 |
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comm.hh
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cpu: Fix o3 front-end pipeline interlock behavior
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2014-09-03 07:42:34 -04:00 |
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commit.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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commit.hh
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cpu: Fix o3 drain bug
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2014-09-03 07:42:45 -04:00 |
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commit_impl.hh
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cpu: Only check for PC events on instruction boundaries.
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2014-12-05 01:47:35 -08:00 |
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cpu.cc
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arch: Make readMiscRegNoEffect const throughout
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2015-02-16 03:33:28 -05:00 |
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cpu.hh
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arch: Make readMiscRegNoEffect const throughout
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2015-02-16 03:33:28 -05:00 |
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cpu_policy.hh
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cpu/o3: clean up rename map and free list
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2013-10-15 14:22:44 -04:00 |
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decode.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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decode.hh
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cpu: Fix o3 front-end pipeline interlock behavior
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2014-09-03 07:42:34 -04:00 |
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decode_impl.hh
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cpu: Fix o3 front-end pipeline interlock behavior
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2014-09-03 07:42:34 -04:00 |
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dep_graph.hh
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cpu: Rewrite O3 draining to avoid stopping in microcode
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2013-01-07 13:05:46 -05:00 |
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deriv.cc
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branch predictor: move out of o3 and inorder cpus
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2013-01-24 12:28:51 -06:00 |
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deriv.hh
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cpu: O3 add a header declaring the DerivO3CPU
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2012-11-02 11:32:01 -05:00 |
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dyn_inst.cc
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O3: Generaize the O3 IMPL class so it isn't split out by ISA.
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2008-10-09 00:10:02 -07:00 |
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dyn_inst.hh
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arch: Use const StaticInstPtr references where possible
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2014-09-27 09:08:36 -04:00 |
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dyn_inst_impl.hh
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arch: Use shared_ptr for all Faults
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2014-10-16 05:49:51 -04:00 |
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fetch.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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fetch.hh
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arch: Pass faults by const reference where possible
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2014-09-19 10:35:18 -04:00 |
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fetch_impl.hh
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mem: Assume all dynamic packet data is array allocated
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2014-12-02 06:07:43 -05:00 |
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free_list.cc
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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free_list.hh
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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fu_pool.cc
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cpu: Consider instructions waiting for FU completion in draining
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2013-06-27 05:49:49 -04:00 |
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fu_pool.hh
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cpu: Consider instructions waiting for FU completion in draining
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2013-06-27 05:49:49 -04:00 |
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FuncUnitConfig.py
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
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FUPool.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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iew.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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iew.hh
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cpu: Fix cache blocked load behavior in o3 cpu
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2014-09-03 07:42:39 -04:00 |
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iew_impl.hh
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cpu: Add drain check functionality to IEW
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2014-10-29 23:18:26 -05:00 |
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impl.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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inst_queue.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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inst_queue.hh
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cpu: Add writeback modeling for drain functionality
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2014-10-29 23:18:27 -05:00 |
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inst_queue_impl.hh
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cpu: Add writeback modeling for drain functionality
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2014-10-29 23:18:27 -05:00 |
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isa_specific.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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lsq.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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lsq.hh
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cpu: Fix cache blocked load behavior in o3 cpu
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2014-09-03 07:42:39 -04:00 |
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lsq_impl.hh
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cpu, o3: Ignored invalidate causing same-address load reordering
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2014-12-02 06:08:03 -05:00 |
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lsq_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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lsq_unit.hh
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arm: Fixes based on UBSan and static analysis
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2014-11-14 03:53:51 -05:00 |
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lsq_unit_impl.hh
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cpu, o3: Ignored invalidate causing same-address load reordering
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2014-12-02 06:08:03 -05:00 |
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mem_dep_unit.cc
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clang: Enable compiling gem5 using clang 2.9 and 3.0
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2012-01-31 12:05:52 -05:00 |
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mem_dep_unit.hh
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cpu: Add drain check functionality to IEW
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2014-10-29 23:18:26 -05:00 |
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mem_dep_unit_impl.hh
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cpu: Add drain check functionality to IEW
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2014-10-29 23:18:26 -05:00 |
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O3Checker.py
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cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
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2013-02-15 17:40:08 -05:00 |
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O3CPU.py
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cpu: Fix SMT scheduling issue with the O3 cpu
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2014-09-03 07:42:37 -04:00 |
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regfile.cc
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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regfile.hh
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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rename.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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rename.hh
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cpu: Use a deque in o3 rename instruction queue
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2014-09-19 10:35:14 -04:00 |
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rename_impl.hh
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cpu: Fix o3 front-end pipeline interlock behavior
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2014-09-03 07:42:34 -04:00 |
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rename_map.cc
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arm: Fixes based on UBSan and static analysis
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2014-11-14 03:53:51 -05:00 |
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rename_map.hh
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arm: Fixes based on UBSan and static analysis
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2014-11-14 03:53:51 -05:00 |
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rob.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
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rob.hh
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cpu: Construct ROB with cpu params struct instead of each variable
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2013-10-31 13:41:13 -05:00 |
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rob_impl.hh
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style: eliminate equality tests with true and false
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2014-05-31 18:00:23 -07:00 |
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SConscript
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cpu: Remove Ozone CPU from the source tree
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2014-10-09 17:51:58 -04:00 |
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SConsopts
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
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scoreboard.cc
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cpu/o3: clean up scoreboard object
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2013-10-15 14:22:43 -04:00 |
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scoreboard.hh
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scons: Fixes uninitialized warnings issued by clang
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2014-03-07 15:56:23 -05:00 |
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store_set.cc
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LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
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2011-08-19 15:08:07 -05:00 |
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store_set.hh
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LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
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2011-08-19 15:08:07 -05:00 |
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thread_context.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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thread_context.hh
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arch: Make readMiscRegNoEffect const throughout
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2015-02-16 03:33:28 -05:00 |
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thread_context_impl.hh
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alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
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2014-09-20 17:18:35 -04:00 |
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thread_state.hh
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arm: Fixes based on UBSan and static analysis
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2014-11-14 03:53:51 -05:00 |
