gem5/src/cpu/inorder
Andreas Sandberg b904bd5437 sim: Add a system-global option to bypass caches
Virtualized CPUs and the fastmem mode of the atomic CPU require direct
access to physical memory. We currently require caches to be disabled
when using them to prevent chaos. This is not ideal when switching
between hardware virutalized CPUs and other CPU models as it would
require a configuration change on each switch. This changeset
introduces a new version of the atomic memory mode,
'atomic_noncaching', where memory accesses are inserted into the
memory system as atomic accesses, but bypass caches.

To make memory mode tests cleaner, the following methods are added to
the System class:

 * isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'.
 * isTimingMode() -- True if the memory mode is 'timing'.
 * bypassCaches() -- True if caches should be bypassed.

The old getMemoryMode() and setMemoryMode() methods should never be
used from the C++ world anymore.
2013-02-15 17:40:09 -05:00
..
resources branch predictor: move out of o3 and inorder cpus 2013-01-24 12:28:51 -06:00
comm.hh Faults: Turn off arch/faults.hh 2012-02-07 04:43:21 -08:00
cpu.cc sim: Add a system-global option to bypass caches 2013-02-15 17:40:09 -05:00
cpu.hh cpu: Refactor memory system checks 2013-02-15 17:40:08 -05:00
first_stage.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
first_stage.hh cpu: Remove unused params.hh header file in inorder CPU 2013-01-07 13:05:45 -05:00
inorder_cpu_builder.cc branch predictor: move out of o3 and inorder cpus 2013-01-24 12:28:51 -06:00
inorder_dyn_inst.cc cpu: rename the misleading inSyscall to noSquashFromTC 2013-01-07 13:05:33 -05:00
inorder_dyn_inst.hh sim: Remove FastAlloc 2012-06-05 01:23:08 -04:00
inorder_trace.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
inorder_trace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
InOrderCPU.py cpu: Add CPU metadata om the Python classes 2013-02-15 17:40:08 -05:00
InOrderTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
pipeline_stage.cc Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
pipeline_stage.hh inorder: implement trap handling 2011-06-19 21:43:36 -04:00
pipeline_traits.5stage.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
pipeline_traits.5stage.hh cpu: Remove unused params.hh header file in inorder CPU 2013-01-07 13:05:45 -05:00
pipeline_traits.9stage.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
pipeline_traits.9stage.hh cpu: Remove unused params.hh header file in inorder CPU 2013-01-07 13:05:45 -05:00
pipeline_traits.9stage.smt2.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
pipeline_traits.9stage.smt2.hh cpu: Remove unused params.hh header file in inorder CPU 2013-01-07 13:05:45 -05:00
pipeline_traits.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
reg_dep_map.cc inorder: clear reg. dep entry after removing from list 2011-06-19 21:43:42 -04:00
reg_dep_map.hh imported patch squash_from_next_stage 2011-06-19 21:43:36 -04:00
resource.cc Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
resource.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
resource_pool.9stage.cc CPU: Round-two unifying instr/data CPU ports across models 2012-02-24 11:42:00 -05:00
resource_pool.cc Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
resource_pool.hh cpu: Remove unused params.hh header file in inorder CPU 2013-01-07 13:05:45 -05:00
resource_sked.cc inorder: addtl functionaly for inst. skeds 2011-06-19 21:43:35 -04:00
resource_sked.hh inorder: addtl functionaly for inst. skeds 2011-06-19 21:43:35 -04:00
SConscript branch predictor: move out of o3 and inorder cpus 2013-01-24 12:28:51 -06:00
SConsopts cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
thread_context.cc cpu: Fix broken thread context handover 2013-01-07 13:05:46 -05:00
thread_context.hh cpu: Unify SimpleCPU and O3 CPU serialization code 2013-01-07 13:05:44 -05:00
thread_state.cc SE/FS: Make the functions available from the TC consistent between SE and FS. 2011-10-31 02:58:22 -07:00
thread_state.hh cpu: rename the misleading inSyscall to noSquashFromTC 2013-01-07 13:05:33 -05:00