gem5/mem
Ali Saidi 8f8d09538f Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working
after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-24 19:31:50 -04:00
..
cache/prefetch Remove unneeded header files. 2006-03-14 18:03:34 -05:00
config Don't forget to check in the needed header file for the conditional prefetch building. 2006-03-16 11:34:19 -05:00
bus.cc make ide disk work for newmem 2006-04-20 17:14:30 -04:00
bus.hh a bit of bad code trampling on memory 2006-04-07 16:26:22 -04:00
mem_object.cc Replace Memory with MemObject; no need for two different levels of hierarchy there. 2006-03-12 17:21:59 -05:00
mem_object.hh Add the bus and connector objects to scons 2006-03-26 21:44:22 -05:00
packet.hh Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
page_table.cc Finally MIPS does hello world! 2006-04-10 12:23:17 -04:00
page_table.hh Take out flags parameter (used for no align fault) 2006-04-10 12:40:07 -04:00
physical.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
physical.hh make ide disk work for newmem 2006-04-20 17:14:30 -04:00
port.cc Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
port.hh fixes for new memory system 2006-04-06 00:51:46 -04:00
request.hh change packet: reset() to resetMin() resetAll() which reset the minium 2006-04-17 14:55:15 -04:00
translating_port.cc Make TranslatingPort be a type of Port rather than something special 2006-03-30 15:59:49 -05:00
translating_port.hh Add a functional port that is used to load the original binaries in FS 2006-03-30 18:06:00 -05:00
vport.cc fixes for new memory system 2006-04-06 00:51:46 -04:00
vport.hh fs now gets to the point where it would really like a filesystem. 2006-04-12 17:46:25 -04:00