gem5/src/arch
Korey Sewell c6d137f565 add Control Bitfield class
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extra : convert_revision : 31e7243c8820cb9f6744c53c417460dee9adaf44
2007-06-22 20:09:46 -04:00
..
alpha Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though. 2007-06-19 18:17:34 +00:00
mips mips import pt. 1 2007-06-22 19:03:42 -04:00
sparc Merge zizzer.eecs.umich.edu:/bk/newmem 2007-06-21 20:35:25 +00:00
x86 Make symbols for regular registers. 2007-06-21 20:35:27 +00:00
isa_parser.py add Control Bitfield class 2007-06-22 20:09:46 -04:00
isa_specific.hh Add build hooks for x86. 2007-03-03 16:01:48 +00:00
micro_asm.py Fix a problem where part of a microops parameters might be interpretted as an "ID", and also added support for symbols. 2007-06-21 15:26:01 +00:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript Merge zizzer.eecs.umich.edu:/bk/newmem 2007-03-15 02:52:51 +00:00