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add Control Bitfield class

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--HG--
extra : convert_revision : 31e7243c8820cb9f6744c53c417460dee9adaf44
This commit is contained in:
Korey Sewell 2007-06-22 20:09:46 -04:00
parent 753adb38d5
commit c6d137f565
1 changed files with 20 additions and 0 deletions
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20
src/arch/isa_parser.py
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@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
# Gabe Black
# Korey Sewell
import os
@ -1410,6 +1411,25 @@ class ControlRegOperand(Operand):
error(0, 'Attempt to write control register as FP')
wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
(self.dest_reg_idx, self.base_name)
class ControlBitfieldOperand(ControlRegOperand):
def makeRead(self):
bit_select = 0
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read control register as FP')
base = 'xc->readMiscReg(%s)' % self.reg_spec
name = self.base_name
return '%s = bits(%s, %s_HI, %s_LO);' % \
(name, base, name, name)
def makeWrite(self):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to write control register as FP')
base = 'xc->readMiscReg(%s)' % self.reg_spec
name = self.base_name
wb_val = 'insertBits(%s, %s_HI, %s_LO, %s)' % \
(base, name, name, self.base_name)
wb = 'xc->setMiscRegOperand(this, %s, %s );\n' % (self.dest_reg_idx, wb_val)
wb += 'if (traceData) { traceData->setData(%s); }' % \
self.base_name
return wb