c27c122afc
change getPort parameter from char* to string Add an extra phase between construction and init called connect SConscript: Add the bus and connector objects to scons cpu/simple/cpu.cc: cpu/simple/cpu.hh: the connection to memory shouldn't be made until we know the memory object exists (e.g. after construction) dev/io_device.hh: change to const string mem/bus.hh: change getPort parameter from char* to string initialize num_interfaces mem/mem_object.hh: change getPort parameter from char* to string mem/physical.cc: mem/physical.hh: change getPort parameter from char* to string get rid of the bus object I created last time python/m5/objects/PhysicalMemory.py: get rid of the bus object I created last time sim/main.cc: sim/sim_object.cc: sim/sim_object.hh: Add an extra phase between construction and init called connect --HG-- extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9 |
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.. | ||
async.hh | ||
builder.cc | ||
builder.hh | ||
byteswap.hh | ||
debug.cc | ||
debug.hh | ||
eventq.cc | ||
eventq.hh | ||
faults.cc | ||
faults.hh | ||
host.hh | ||
main.cc | ||
param.cc | ||
param.hh | ||
process.cc | ||
process.hh | ||
pseudo_inst.cc | ||
pseudo_inst.hh | ||
root.cc | ||
serialize.cc | ||
serialize.hh | ||
sim_events.cc | ||
sim_events.hh | ||
sim_exit.hh | ||
sim_object.cc | ||
sim_object.hh | ||
startup.cc | ||
startup.hh | ||
stat_control.cc | ||
stat_control.hh | ||
stats.hh | ||
syscall_emul.cc | ||
syscall_emul.hh | ||
system.cc | ||
system.hh | ||
vptr.hh |