Nilay Vaish bb6d7d402b ruby: rename MESI_CMP_directory to MESI_Two_Level ... This is because the next patch introduces a three level hierarchy. --HG-- rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt		2014-01-04 00:03:33 -06:00
..
cache	cpu: add consistent guarding to *_impl.hh files.	2013-10-17 10:20:45 -05:00
protocol	ruby: rename MESI_CMP_directory to MESI_Two_Level	2014-01-04 00:03:33 -06:00
ruby	ruby: add support for clusters	2014-01-04 00:03:31 -06:00
slicc	ruby: add support for clusters	2014-01-04 00:03:31 -06:00
abstract_mem.cc	mem: Make MemoryAccess flag more verbose	2013-10-17 10:20:45 -05:00
abstract_mem.hh	mem: Avoid explicitly zeroing the memory backing store	2013-05-30 12:53:54 -04:00
AbstractMemory.py	mem: Change AbstractMemory defaults to match the common case	2013-08-19 03:52:33 -04:00
addr_mapper.cc	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
addr_mapper.hh	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
AddrMapper.py	sim: Include object header files in SWIG interfaces	2012-11-02 11:32:01 -05:00
bridge.cc	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
bridge.hh	mem: Tidy up the bridge with const and additional checks	2013-06-27 05:49:49 -04:00
Bridge.py	mem: Tidy up the bridge with const and additional checks	2013-06-27 05:49:49 -04:00
bus.cc	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
bus.hh	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
Bus.py	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
coherent_bus.cc	mem: Make returning snoop responses occupy response layer	2013-05-30 12:54:02 -04:00
coherent_bus.hh	mem: De-virtualise interfaces in the CoherentBus	2013-10-17 10:20:45 -05:00
comm_monitor.cc	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
comm_monitor.hh	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
CommMonitor.py	mem: Add tracing support in the communication monitor	2013-01-07 13:05:37 -05:00
fs_translating_port_proxy.cc	arch: Resurrect the NOISA build target and rename it NULL	2013-09-04 13:22:57 -04:00
fs_translating_port_proxy.hh	arch: Resurrect the NOISA build target and rename it NULL	2013-09-04 13:22:57 -04:00
mem_object.cc	Port: Add protocol-agnostic ports in the port hierarchy	2012-10-15 08:12:35 -04:00
mem_object.hh	Port: Add protocol-agnostic ports in the port hierarchy	2012-10-15 08:12:35 -04:00
MemObject.py	sim: Include object header files in SWIG interfaces	2012-11-02 11:32:01 -05:00
mport.cc	MEM: Separate snoops and normal memory requests/responses	2012-04-14 05:45:07 -04:00
mport.hh	MEM: Separate requests and responses for timing accesses	2012-05-01 13:40:42 -04:00
noncoherent_bus.cc	mem: Make the buses multi layered	2013-05-30 12:54:01 -04:00
noncoherent_bus.hh	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
packet.cc	mem: Adding verbose debug output in the memory system	2013-04-22 13:20:33 -04:00
packet.hh	mem: Add "const" attribute to Packet getters	2013-10-31 13:41:13 -05:00
packet_access.hh	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	2009-09-23 08:34:21 -07:00
packet_queue.cc	mem: Adding verbose debug output in the memory system	2013-04-22 13:20:33 -04:00
packet_queue.hh	sim: have a curTick per eventq	2012-11-16 10:27:47 -06:00
page_table.cc	sim: Fix two bugs relating to software caching of PageTable entries.	2013-04-23 09:47:52 -04:00
page_table.hh	sim: Fix two bugs relating to software caching of PageTable entries.	2013-04-23 09:47:52 -04:00
physical.cc	mem: Avoid explicitly zeroing the memory backing store	2013-05-30 12:53:54 -04:00
physical.hh	mem: Merge ranges that are part of the conf table	2013-01-07 13:05:38 -05:00
port.cc	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
port.hh	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
port_proxy.cc	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
port_proxy.hh	arch: Resurrect the NOISA build target and rename it NULL	2013-09-04 13:22:57 -04:00
qport.hh	mem: Add PortID to QueuedMasterPort constructor	2013-10-17 10:20:45 -05:00
request.hh	mem: Add privilege info to request class	2013-10-31 13:41:13 -05:00
SConscript	mem: Use the same timing calculation for DRAM read and write	2013-11-01 11:56:19 -04:00
se_translating_port_proxy.cc	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
se_translating_port_proxy.hh	MEM: Introduce the master/slave port sub-classes in C++	2012-03-30 09:40:11 -04:00
simple_dram.cc	mem: Fixes for DRAM stats accounting	2013-11-01 11:56:31 -04:00
simple_dram.hh	mem: Fixes for DRAM stats accounting	2013-11-01 11:56:31 -04:00
simple_mem.cc	mem: Fix scheduling bug in SimpleMemory	2013-09-18 08:46:33 -04:00
simple_mem.hh	mem: Add an internal packet queue in SimpleMemory	2013-08-19 03:52:25 -04:00
SimpleDRAM.py	mem: Fix the LPDDR3 page size	2013-11-01 11:56:30 -04:00
SimpleMemory.py	mem: Add an internal packet queue in SimpleMemory	2013-08-19 03:52:25 -04:00
tport.cc	mem: Replace check with panic where inhibited should not happen	2013-04-22 13:20:33 -04:00
tport.hh	Port: Hide the queue implementation in SimpleTimingPort	2012-07-09 12:35:42 -04:00