ruby: add support for clusters
A cluster over here means a set of controllers that can be accessed only by a certain set of cores. For example, consider a two level hierarchy. Assume there are 4 L1 controllers (private) and 2 L2 controllers. We can have two different hierarchies here: a. the address space is partitioned between the two L2 controllers. Each L1 controller accesses both the L2 controllers. In this case, each L1 controller is a cluster initself. b. both the L2 controllers can cache any address. An L1 controller has access to only one of the L2 controllers. In this case, each L2 controller along with the L1 controllers that access it, form a cluster. This patch allows for each controller to have a cluster ID, which is 0 by default. By setting the cluster ID properly, one can instantiate hierarchies with clusters. Note that the coherence protocol might have to be changed as well.
This commit is contained in:
parent
9853ef6651
commit
5b1804e3bd
16 changed files with 107 additions and 110 deletions
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@ -500,7 +500,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Type := CoherenceRequestType:GETS;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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DPRINTF(RubySlicc, "address: %s, destination: %s\n",
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address, out_msg.Destination);
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out_msg.MessageSize := MessageSizeType:Control;
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@ -518,7 +518,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Type := CoherenceRequestType:GETS;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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DPRINTF(RubySlicc, "address: %s, destination: %s\n",
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address, out_msg.Destination);
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out_msg.MessageSize := MessageSizeType:Control;
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@ -535,7 +535,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Type := CoherenceRequestType:GET_INSTR;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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DPRINTF(RubySlicc, "address: %s, destination: %s\n",
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address, out_msg.Destination);
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out_msg.MessageSize := MessageSizeType:Control;
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@ -555,7 +555,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Requestor := machineID;
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out_msg.Destination.add(
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mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Control;
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out_msg.Prefetch := in_msg.Prefetch;
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out_msg.AccessMode := in_msg.AccessMode;
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@ -574,7 +574,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Requestor := machineID;
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DPRINTF(RubySlicc, "%s\n", machineID);
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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DPRINTF(RubySlicc, "address: %s, destination: %s\n",
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address, out_msg.Destination);
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out_msg.MessageSize := MessageSizeType:Control;
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@ -593,10 +593,8 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Requestor := machineID;
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DPRINTF(RubySlicc, "%s\n", machineID);
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out_msg.Destination.add(mapAddressToRange(address,
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MachineType:L2Cache,
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l2_select_low_bit,
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l2_select_num_bits));
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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DPRINTF(RubySlicc, "address: %s, destination: %s\n",
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address, out_msg.Destination);
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@ -614,7 +612,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Type := CoherenceRequestType:UPGRADE;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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DPRINTF(RubySlicc, "address: %s, destination: %s\n",
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address, out_msg.Destination);
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out_msg.MessageSize := MessageSizeType:Control;
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@ -648,7 +646,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Dirty := cache_entry.Dirty;
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out_msg.Sender := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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@ -677,7 +675,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Dirty := tbe.Dirty;
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out_msg.Sender := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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@ -703,7 +701,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Dirty := cache_entry.Dirty;
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out_msg.Sender := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Writeback_Data;
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}
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}
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@ -717,7 +715,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Dirty := tbe.Dirty;
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out_msg.Sender := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Writeback_Data;
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}
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}
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@ -751,7 +749,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Dirty := cache_entry.Dirty;
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out_msg.Requestor:= machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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if (cache_entry.Dirty) {
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out_msg.MessageSize := MessageSizeType:Writeback_Data;
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} else {
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@ -766,7 +764,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Type := CoherenceResponseType:UNBLOCK;
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out_msg.Sender := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Response_Control;
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DPRINTF(RubySlicc, "%s\n", address);
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}
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@ -778,7 +776,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
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out_msg.Sender := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Response_Control;
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DPRINTF(RubySlicc, "%s\n", address);
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@ -39,7 +39,6 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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MemoryControl * memBuffer,
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Cycles to_mem_ctrl_latency = 1,
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Cycles directory_latency = 6,
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int l2_select_num_bits
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{
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MessageBuffer requestToDir, network="From", virtual_network="0",
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ordered="false", vnet_type="request";
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@ -83,6 +82,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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structure(Entry, desc="...", interface="AbstractEntry") {
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State DirectoryState, desc="Directory state";
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DataBlock DataBlk, desc="data for the block";
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MachineID Owner;
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}
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// TBE entries for DMA requests
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@ -102,8 +102,6 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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// ** OBJECTS **
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int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
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TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
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void set_tbe(TBE tbe);
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@ -262,6 +260,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Dirty := false;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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Entry e := getDirectoryEntry(in_msg.Addr);
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e.Owner := in_msg.OriginalRequestorMachId;
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}
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}
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}
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@ -409,12 +410,11 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {
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out_msg.Addr := address;
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out_msg.Type := CoherenceResponseType:INV;
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out_msg.Sender := machineID;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Response_Control;
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out_msg.Addr := address;
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out_msg.Type := CoherenceResponseType:INV;
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out_msg.Sender := machineID;
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out_msg.Destination.add(getDirectoryEntry(address).Owner);
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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}
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@ -483,6 +483,11 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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j_popIncomingRequestQueue;
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}
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transition(M, Fetch) {
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inv_sendCacheInvalidate;
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z_stallAndWaitRequest;
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}
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transition(IM, Memory_Data, M) {
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d_sendData;
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l_popMemQueue;
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@ -492,6 +497,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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transition(M, CleanReplacement, I) {
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a_sendAck;
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k_popIncomingResponseQueue;
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kd_wakeUpDependents;
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}
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transition(M, Data, MI) {
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@ -578,5 +584,4 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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l_popMemQueue;
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kd_wakeUpDependents;
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}
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}
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@ -420,7 +420,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Requestor := machineID;
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out_msg.RequestorMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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out_msg.AccessMode := in_msg.AccessMode;
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out_msg.Prefetch := in_msg.Prefetch;
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@ -436,7 +436,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Requestor := machineID;
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out_msg.RequestorMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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out_msg.AccessMode := in_msg.AccessMode;
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out_msg.Prefetch := in_msg.Prefetch;
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@ -452,7 +452,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Requestor := machineID;
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out_msg.RequestorMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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@ -465,7 +465,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Requestor := machineID;
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out_msg.RequestorMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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@ -478,7 +478,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Requestor := machineID;
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out_msg.RequestorMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.DataBlk := cache_entry.DataBlk;
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// out_msg.Dirty := cache_entry.Dirty;
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out_msg.Dirty := false;
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@ -528,7 +528,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.Dirty := cache_entry.Dirty;
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out_msg.Acks := 0; // irrelevant
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@ -546,7 +546,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.Dirty := cache_entry.Dirty;
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out_msg.Acks := in_msg.Acks;
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@ -591,7 +591,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.Acks := 0 - 1; // -1
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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@ -606,7 +606,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Unblock_Control;
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}
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}
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@ -618,7 +618,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.MessageSize := MessageSizeType:Unblock_Control;
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}
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}
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@ -715,7 +715,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.Dirty := false;
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out_msg.Acks := 1;
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out_msg.MessageSize := MessageSizeType:Response_Control;
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@ -748,7 +748,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.DataBlk := tbe.DataBlk;
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// out_msg.Dirty := tbe.Dirty;
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out_msg.Dirty := false;
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@ -782,7 +782,7 @@ machine(L1Cache, "Directory protocol")
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
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l2_select_low_bit, l2_select_num_bits));
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l2_select_low_bit, l2_select_num_bits, intToID(0)));
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out_msg.DataBlk := tbe.DataBlk;
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out_msg.Dirty := tbe.Dirty;
|
||||
out_msg.Acks := in_msg.Acks;
|
||||
|
@ -800,7 +800,7 @@ machine(L1Cache, "Directory protocol")
|
|||
out_msg.Sender := machineID;
|
||||
out_msg.SenderMachine := MachineType:L1Cache;
|
||||
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
|
||||
l2_select_low_bit, l2_select_num_bits));
|
||||
l2_select_low_bit, l2_select_num_bits, intToID(0)));
|
||||
out_msg.Dirty := tbe.Dirty;
|
||||
if (tbe.Dirty) {
|
||||
out_msg.Type := CoherenceResponseType:WRITEBACK_DIRTY_DATA;
|
||||
|
|
|
@ -406,7 +406,7 @@ machine(L1Cache, "Token protocol")
|
|||
} else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
|
||||
|
||||
if (sender == mapAddressToRange(addr, MachineType:L2Cache,
|
||||
l2_select_low_bit, l2_select_num_bits)) {
|
||||
l2_select_low_bit, l2_select_num_bits, intToID(0))) {
|
||||
return false;
|
||||
} else {
|
||||
return true;
|
||||
|
@ -540,9 +540,8 @@ machine(L1Cache, "Token protocol")
|
|||
if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
|
||||
|
||||
if (in_msg.Sender == mapAddressToRange(in_msg.Addr,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits)) {
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0))) {
|
||||
|
||||
// came from an off-chip L2 cache
|
||||
if (is_valid(tbe)) {
|
||||
|
@ -748,9 +747,8 @@ machine(L1Cache, "Token protocol")
|
|||
//out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.Destination.add(map_Address_to_Directory(address));
|
||||
out_msg.MessageSize := MessageSizeType:Persistent_Control;
|
||||
|
@ -792,9 +790,8 @@ machine(L1Cache, "Token protocol")
|
|||
out_msg.Type := CoherenceRequestType:GETS;
|
||||
out_msg.Requestor := machineID;
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.RetryNum := tbe.IssueCount;
|
||||
if (tbe.IssueCount == 0) {
|
||||
|
@ -869,9 +866,8 @@ machine(L1Cache, "Token protocol")
|
|||
//out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.Destination.add(map_Address_to_Directory(address));
|
||||
out_msg.MessageSize := MessageSizeType:Persistent_Control;
|
||||
|
@ -914,9 +910,8 @@ machine(L1Cache, "Token protocol")
|
|||
out_msg.Requestor := machineID;
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.RetryNum := tbe.IssueCount;
|
||||
|
||||
|
@ -991,9 +986,8 @@ machine(L1Cache, "Token protocol")
|
|||
out_msg.Sender := machineID;
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.Tokens := cache_entry.Tokens;
|
||||
out_msg.DataBlk := cache_entry.DataBlk;
|
||||
|
@ -1016,9 +1010,8 @@ machine(L1Cache, "Token protocol")
|
|||
out_msg.Sender := machineID;
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.Tokens := cache_entry.Tokens;
|
||||
out_msg.DataBlk := cache_entry.DataBlk;
|
||||
|
@ -1039,9 +1032,8 @@ machine(L1Cache, "Token protocol")
|
|||
out_msg.Sender := machineID;
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.Tokens := cache_entry.Tokens;
|
||||
out_msg.DataBlk := cache_entry.DataBlk;
|
||||
|
@ -1384,10 +1376,8 @@ machine(L1Cache, "Token protocol")
|
|||
out_msg.Sender := machineID;
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
out_msg.MessageSize := MessageSizeType:Response_Control;
|
||||
}
|
||||
}
|
||||
|
@ -1427,9 +1417,8 @@ machine(L1Cache, "Token protocol")
|
|||
//out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.Destination.add(map_Address_to_Directory(address));
|
||||
out_msg.MessageSize := MessageSizeType:Persistent_Control;
|
||||
|
|
|
@ -443,9 +443,8 @@ machine(Directory, "Token protocol")
|
|||
//out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.Destination.add(map_Address_to_Directory(address));
|
||||
out_msg.MessageSize := MessageSizeType:Persistent_Control;
|
||||
|
@ -485,9 +484,8 @@ machine(Directory, "Token protocol")
|
|||
//
|
||||
out_msg.Destination.broadcast(MachineType:L1Cache);
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.RetryNum := 0;
|
||||
out_msg.MessageSize := MessageSizeType:Broadcast_Control;
|
||||
|
@ -513,9 +511,8 @@ machine(Directory, "Token protocol")
|
|||
//out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.Destination.add(map_Address_to_Directory(address));
|
||||
out_msg.MessageSize := MessageSizeType:Persistent_Control;
|
||||
|
@ -551,9 +548,8 @@ machine(Directory, "Token protocol")
|
|||
//
|
||||
out_msg.Destination.broadcast(MachineType:L1Cache);
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.RetryNum := 0;
|
||||
out_msg.MessageSize := MessageSizeType:Broadcast_Control;
|
||||
|
@ -730,9 +726,8 @@ machine(Directory, "Token protocol")
|
|||
//out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
|
||||
|
||||
out_msg.Destination.add(mapAddressToRange(address,
|
||||
MachineType:L2Cache,
|
||||
l2_select_low_bit,
|
||||
l2_select_num_bits));
|
||||
MachineType:L2Cache, l2_select_low_bit,
|
||||
l2_select_num_bits, intToID(0)));
|
||||
|
||||
out_msg.Destination.add(map_Address_to_Directory(address));
|
||||
out_msg.MessageSize := MessageSizeType:Persistent_Control;
|
||||
|
|
|
@ -30,7 +30,8 @@
|
|||
// Mapping functions
|
||||
|
||||
int machineCount(MachineType machType);
|
||||
MachineID mapAddressToRange(Address addr, MachineType type, int low, int high);
|
||||
MachineID mapAddressToRange(Address addr, MachineType type,
|
||||
int low, int high, NodeID n);
|
||||
NetDest broadcast(MachineType type);
|
||||
MachineID map_Address_to_DMA(Address addr);
|
||||
MachineID map_Address_to_Directory(Address addr);
|
||||
|
|
|
@ -31,4 +31,4 @@
|
|||
NodeID id;
|
||||
NodeID version;
|
||||
MachineID machineID;
|
||||
|
||||
NodeID clusterID;
|
||||
|
|
|
@ -102,7 +102,7 @@ NetDest::broadcast()
|
|||
void
|
||||
NetDest::broadcast(MachineType machineType)
|
||||
{
|
||||
for (int i = 0; i < MachineType_base_count(machineType); i++) {
|
||||
for (NodeID i = 0; i < MachineType_base_count(machineType); i++) {
|
||||
MachineID mach = {machineType, i};
|
||||
add(mach);
|
||||
}
|
||||
|
@ -146,7 +146,7 @@ NetDest::smallestElement() const
|
|||
{
|
||||
assert(count() > 0);
|
||||
for (int i = 0; i < m_bits.size(); i++) {
|
||||
for (int j = 0; j < m_bits[i].getSize(); j++) {
|
||||
for (NodeID j = 0; j < m_bits[i].getSize(); j++) {
|
||||
if (m_bits[i].isElement(j)) {
|
||||
MachineID mach = {MachineType_from_base_level(i), j};
|
||||
return mach;
|
||||
|
@ -160,7 +160,7 @@ MachineID
|
|||
NetDest::smallestElement(MachineType machine) const
|
||||
{
|
||||
int size = m_bits[MachineType_base_level(machine)].getSize();
|
||||
for (int j = 0; j < size; j++) {
|
||||
for (NodeID j = 0; j < size; j++) {
|
||||
if (m_bits[MachineType_base_level(machine)].isElement(j)) {
|
||||
MachineID mach = {machine, j};
|
||||
return mach;
|
||||
|
|
|
@ -37,8 +37,8 @@ typedef int64 Time;
|
|||
typedef uint64 physical_address_t;
|
||||
|
||||
typedef int64 Index; // what the address bit ripper returns
|
||||
typedef int LinkID;
|
||||
typedef int NodeID;
|
||||
typedef int SwitchID;
|
||||
typedef unsigned int LinkID;
|
||||
typedef unsigned int NodeID;
|
||||
typedef unsigned int SwitchID;
|
||||
|
||||
#endif
|
||||
|
|
|
@ -129,7 +129,7 @@ Topology::createLinks(Network *net)
|
|||
SwitchID max_switch_id = 0;
|
||||
for (LinkMap::const_iterator i = m_link_map.begin();
|
||||
i != m_link_map.end(); ++i) {
|
||||
std::pair<int, int> src_dest = (*i).first;
|
||||
std::pair<SwitchID, SwitchID> src_dest = (*i).first;
|
||||
max_switch_id = max(max_switch_id, src_dest.first);
|
||||
max_switch_id = max(max_switch_id, src_dest.second);
|
||||
}
|
||||
|
@ -310,7 +310,7 @@ shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights,
|
|||
max_machines = MachineType_base_number(MachineType_NUM);
|
||||
|
||||
for (int m = 0; m < machines; m++) {
|
||||
for (int i = 0; i < MachineType_base_count((MachineType)m); i++) {
|
||||
for (NodeID i = 0; i < MachineType_base_count((MachineType)m); i++) {
|
||||
// we use "d+max_machines" below since the "destination"
|
||||
// switches for the machines are numbered
|
||||
// [MachineType_base_number(MachineType_NUM)...
|
||||
|
|
|
@ -59,7 +59,7 @@ struct LinkEntry
|
|||
LinkDirection direction;
|
||||
};
|
||||
|
||||
typedef std::map<std::pair<int, int>, LinkEntry> LinkMap;
|
||||
typedef std::map<std::pair<SwitchID, SwitchID>, LinkEntry> LinkMap;
|
||||
|
||||
class Topology
|
||||
{
|
||||
|
|
|
@ -35,6 +35,8 @@ AbstractController::AbstractController(const Params *p)
|
|||
m_request_count(0)
|
||||
{
|
||||
m_version = p->version;
|
||||
m_clusterID = p->cluster_id;
|
||||
|
||||
m_transitions_per_cycle = p->transitions_per_cycle;
|
||||
m_buffer_size = p->buffer_size;
|
||||
m_recycle_latency = p->recycle_latency;
|
||||
|
|
|
@ -56,7 +56,7 @@ class AbstractController : public ClockedObject, public Consumer
|
|||
void init();
|
||||
const Params *params() const { return (const Params *)_params; }
|
||||
|
||||
const int & getVersion() const { return m_version; }
|
||||
const NodeID getVersion() const { return m_version; }
|
||||
void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
|
||||
|
||||
// return instance name
|
||||
|
@ -133,13 +133,12 @@ class AbstractController : public ClockedObject, public Consumer
|
|||
void wakeUpAllBuffers();
|
||||
|
||||
protected:
|
||||
int m_transitions_per_cycle;
|
||||
int m_buffer_size;
|
||||
Cycles m_recycle_latency;
|
||||
std::string m_name;
|
||||
NodeID m_version;
|
||||
Network* m_net_ptr;
|
||||
MachineID m_machineID;
|
||||
NodeID m_clusterID;
|
||||
|
||||
Network* m_net_ptr;
|
||||
bool m_is_blocking;
|
||||
std::map<Address, MessageBuffer*> m_block_map;
|
||||
typedef std::vector<MessageBuffer*> MsgVecType;
|
||||
|
@ -148,6 +147,9 @@ class AbstractController : public ClockedObject, public Consumer
|
|||
unsigned int m_in_ports;
|
||||
unsigned int m_cur_in_port;
|
||||
int m_number_of_TBEs;
|
||||
int m_transitions_per_cycle;
|
||||
int m_buffer_size;
|
||||
Cycles m_recycle_latency;
|
||||
|
||||
//! Map from physical network number to the Message Buffer.
|
||||
std::map<uint32_t, MessageBuffer*> peerQueueMap;
|
||||
|
|
|
@ -36,7 +36,8 @@ class RubyController(ClockedObject):
|
|||
cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
|
||||
abstract = True
|
||||
version = Param.Int("")
|
||||
cntrl_id = Param.Int("")
|
||||
cluster_id = Param.UInt32(0, "Id of this controller's cluster")
|
||||
|
||||
transitions_per_cycle = \
|
||||
Param.Int(32, "no. of SLICC state machine transitions per cycle")
|
||||
buffer_size = Param.Int(0, "max buffer size 0 means infinite")
|
||||
|
|
|
@ -58,7 +58,7 @@ inline NetDest
|
|||
broadcast(MachineType type)
|
||||
{
|
||||
NetDest dest;
|
||||
for (int i = 0; i < MachineType_base_count(type); i++) {
|
||||
for (NodeID i = 0; i < MachineType_base_count(type); i++) {
|
||||
MachineID mach = {type, i};
|
||||
dest.add(mach);
|
||||
}
|
||||
|
@ -67,12 +67,14 @@ broadcast(MachineType type)
|
|||
|
||||
inline MachineID
|
||||
mapAddressToRange(const Address & addr, MachineType type, int low_bit,
|
||||
int num_bits)
|
||||
int num_bits, int cluster_id = 0)
|
||||
{
|
||||
MachineID mach = {type, 0};
|
||||
if (num_bits == 0)
|
||||
return mach;
|
||||
mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1);
|
||||
mach.num = cluster_id;
|
||||
else
|
||||
mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1)
|
||||
+ (1 << num_bits) * cluster_id;
|
||||
return mach;
|
||||
}
|
||||
|
||||
|
|
|
@ -70,6 +70,8 @@ class ObjDeclAST(DeclAST):
|
|||
c_code = "m_version"
|
||||
elif self.ident == "machineID":
|
||||
c_code = "m_machineID"
|
||||
elif self.ident == "clusterID":
|
||||
c_code = "m_clusterID"
|
||||
elif machine:
|
||||
c_code = "(*m_%s_%s_ptr)" % (machine.ident, self.ident)
|
||||
else:
|
||||
|
|
Loading…
Reference in a new issue