Geoffrey Blake af6aaf2581 CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 ... Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification.		2012-01-31 07:46:03 -08:00
..
decoder	ARM: Add support for M5 ops in the ARM ISA	2010-11-08 13:58:24 -06:00
formats	GCC: Get everything working with gcc 4.6.1.	2011-10-31 01:09:44 -07:00
insts	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	2012-01-31 07:46:03 -08:00
templates	GCC: Get everything working with gcc 4.6.1.	2011-10-31 01:09:44 -07:00
bitfields.isa	ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.	2010-06-02 12:58:07 -05:00
copyright.txt	ARM: Remove IsControl from operands that don't imply control transfers.	2010-06-02 12:57:59 -05:00
includes.isa	ISA: Use readBytes/writeBytes for all instruction level memory operations.	2011-07-02 22:34:29 -07:00
main.isa	ARM: Define the load instructions from outside the decoder.	2010-06-02 12:58:01 -05:00
operands.isa	ISA parser: Define operand types with a ctype directly.	2011-07-05 16:52:15 -07:00