gem5/src/mem
Andreas Hansson a6074016e2 Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.

The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).

As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.

A bit of tidying up has also been done as part of the simplifications.

Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 11:39:58 -04:00
..
cache Port: Extend the QueuedPort interface and use where appropriate 2012-08-22 11:39:56 -04:00
config Fixes to get prefetching working again. 2009-02-16 08:56:40 -08:00
protocol Ruby: remove some unused stuff from SLICC files 2012-07-12 08:39:18 -05:00
ruby Port: Extend the QueuedPort interface and use where appropriate 2012-08-22 11:39:56 -04:00
slicc imported patch jason/slicc-external-structure-fix 2012-07-10 22:51:54 -07:00
abstract_mem.cc Mem: Make members relating to range and size constant 2012-07-09 12:35:44 -04:00
abstract_mem.hh Mem: Make members relating to range and size constant 2012-07-09 12:35:44 -04:00
AbstractMemory.py MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
bridge.cc Bridge: Remove NACKs in the bridge and unify with packet queue 2012-08-22 11:39:58 -04:00
bridge.hh Bridge: Remove NACKs in the bridge and unify with packet queue 2012-08-22 11:39:58 -04:00
Bridge.py Bridge: Remove NACKs in the bridge and unify with packet queue 2012-08-22 11:39:58 -04:00
bus.cc Clock: Move the clock and related functions to ClockedObject 2012-08-21 05:49:01 -04:00
bus.hh Clock: Move the clock and related functions to ClockedObject 2012-08-21 05:49:01 -04:00
Bus.py Clock: Move the clock and related functions to ClockedObject 2012-08-21 05:49:01 -04:00
coherent_bus.cc Port: Align port names in C++ and Python 2012-07-09 12:35:39 -04:00
coherent_bus.hh Bus: Split the bus into separate request/response layers 2012-07-09 12:35:37 -04:00
comm_monitor.cc Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
comm_monitor.hh Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
CommMonitor.py MEM: Add the communication monitor 2012-05-09 04:37:45 -04:00
fs_translating_port_proxy.cc mem: fix bug with CopyStringOut and null string termination. 2012-05-10 18:04:27 -05:00
fs_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.cc Clock: Move the clock and related functions to ClockedObject 2012-08-21 05:49:01 -04:00
mem_object.hh Clock: Move the clock and related functions to ClockedObject 2012-08-21 05:49:01 -04:00
MemObject.py Clock: Move the clock and related functions to ClockedObject 2012-08-21 05:49:01 -04:00
mport.cc MEM: Separate snoops and normal memory requests/responses 2012-04-14 05:45:07 -04:00
mport.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
noncoherent_bus.cc Port: Align port names in C++ and Python 2012-07-09 12:35:39 -04:00
noncoherent_bus.hh Bus: Split the bus into separate request/response layers 2012-07-09 12:35:37 -04:00
packet.cc Packet: Cleaning up packet command and attribute 2012-05-23 09:18:04 -04:00
packet.hh sim: Remove FastAlloc 2012-06-05 01:23:08 -04:00
packet_access.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
packet_queue.cc Port: Extend the QueuedPort interface and use where appropriate 2012-08-22 11:39:56 -04:00
packet_queue.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
page_table.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
page_table.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
physical.cc MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
physical.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
port.cc O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs 2012-08-15 10:38:08 -04:00
port.hh O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs 2012-08-15 10:38:08 -04:00
port_proxy.cc MEM: Remove the Broadcast destination from the packet 2012-04-14 05:45:55 -04:00
port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
qport.hh Port: Extend the QueuedPort interface and use where appropriate 2012-08-22 11:39:56 -04:00
request.hh sim: Remove FastAlloc 2012-06-05 01:23:08 -04:00
SConscript Bridge: Remove NACKs in the bridge and unify with packet queue 2012-08-22 11:39:58 -04:00
se_translating_port_proxy.cc SETranslatingPortProxy: fix bug in tryReadString() 2012-08-06 16:57:11 -07:00
se_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
simple_mem.cc Mem: Make SimpleMemory single ported 2012-07-12 12:56:13 -04:00
simple_mem.hh Mem: Make SimpleMemory single ported 2012-07-12 12:56:13 -04:00
SimpleMemory.py Mem: Make SimpleMemory single ported 2012-07-12 12:56:13 -04:00
tport.cc Port: Extend the QueuedPort interface and use where appropriate 2012-08-22 11:39:56 -04:00
tport.hh Port: Hide the queue implementation in SimpleTimingPort 2012-07-09 12:35:42 -04:00