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gem5/src/arch/power
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Curtis Dunham 7f1603d207 arch: remove inline specifiers on all inst constrs, all ISAs 
With (upcoming) separate compilation, they are useless.  Only
link-time optimization could re-inline them, but ideally
feedback-directed optimization would choose to do so only for
profitable (i.e. common) instructions.
2014-05-09 18:58:46 -04:00
..
insts cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00
isa arch: remove inline specifiers on all inst constrs, all ISAs 2014-05-09 18:58:46 -04:00
linux scons: Add warning for overloaded virtual functions 2013-02-19 05:56:06 -05:00
decoder.cc ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
decoder.hh x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch 2013-01-22 00:10:10 -06:00
faults.hh Faults: Replace calls to genMachineCheckFault with M5PanicFault. 2011-09-27 00:24:43 -07:00
interrupts.cc SE/FS: Build the Interrupt objects in SE mode. 2011-10-09 00:15:50 -07:00
interrupts.hh SE/FS: Build the Interrupt objects in SE mode. 2011-10-09 00:15:50 -07:00
isa.cc arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
isa.hh arch: Make all register index flattening const 2014-01-24 15:29:30 -06:00
isa_traits.hh ISA: generic Linux thread info support 2012-11-02 11:32:00 -05:00
kernel_stats.hh Power: Add a stub kernel_stats.hh. 2011-11-13 12:40:15 -08:00
locked_mem.hh cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped. 2014-01-24 15:29:30 -06:00
microcode_rom.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
miscregs.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
mmapped_ipr.hh arch: Add support for m5ops using mmapped IPRs 2013-09-30 12:20:43 +02:00
pagetable.cc Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
pagetable.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
PowerInterrupts.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
PowerISA.py arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
PowerTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
process.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
process.hh scons: Add warning for overloaded virtual functions 2013-02-19 05:56:06 -05:00
registers.hh cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00
remote_gdb.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
SConscript arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
SConsopts POWER: Add support for the Power ISA 2009-10-27 09:24:39 -07:00
stacktrace.cc Power: Add a stubbed out stacktrace.cc 2011-11-13 12:40:15 -08:00
stacktrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
tlb.cc arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
tlb.hh arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
types.hh clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6 2012-04-14 05:43:31 -04:00
utility.cc cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00
utility.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
vtophys.cc Implement Ali's review feedback. 2012-01-29 02:04:34 -08:00
vtophys.hh Merge with main repository. 2012-01-30 21:07:57 -08:00