Ron Dreslinski 567afbf6ce More cache fixes. Atomic coherence now works as well. ... src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Make Memtester able to test atomic as well src/mem/bus.cc: src/mem/bus.hh: Handle atomic snoops properly for cache->cache transfers src/mem/cache/cache_impl.hh: Debug output. Clean up memleak in atomic mode. Set hitLatency. Still need to send back reasonable number for atomic return value. src/mem/packet.cc: Add command strings for new commands src/python/m5/objects/MemTest.py: Add param to test atomic memory. --HG-- extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b		2006-10-11 18:28:33 -04:00
..
coherence	Fix how upgrades work.	2006-10-09 19:15:24 -04:00
miss	Fix some more mem leaks, still some left	2006-10-10 17:10:56 -04:00
prefetch	Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.	2006-08-15 16:21:46 -04:00
tags	Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches.	2006-08-15 16:21:46 -04:00
base_cache.cc	Use bus response time paramteres	2006-10-11 01:01:40 -04:00
base_cache.hh	Some more code cleanup	2006-10-10 17:25:50 -04:00
cache.cc	Was having difficulty with merging the cache, reverted to an early version and will add back in the patches to make it work soon.	2006-06-28 11:02:14 -04:00
cache.hh	Fix several bugs pertaining to upgrades/mem leaks.	2006-10-10 01:32:18 -04:00
cache_blk.hh	#include of iostream needed.	2006-08-11 20:23:31 -04:00
cache_builder.cc	Fix the packet data allocation methods. Small fixes from changesets after my initial work.	2006-06-30 11:34:27 -04:00
cache_impl.hh	More cache fixes. Atomic coherence now works as well.	2006-10-11 18:28:33 -04:00