gem5/arch/alpha
Kevin Lim 716ceb6c10 Code update for CPU models.
arch/alpha/isa_traits.hh:
    Add in clear functions.
cpu/base.cc:
cpu/base.hh:
    Add in CPU progress event.
cpu/base_dyn_inst.hh:
    Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
    Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
    Allow for progress intervals.
cpu/o3/tournament_pred.cc:
    Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
    Fixes.
cpu/ozone/cpu_builder.cc:
    Allow progress interval.
cpu/ozone/front_end_impl.hh:
    Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
    Remove this.
python/m5/objects/BaseCPU.py:
    Add progress interval.
python/m5/objects/Root.py:
    Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
    Add in stats reset.

--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e
2006-08-11 17:42:59 -04:00
..
freebsd Merge ktlim@zizzer:/bk/m5 2006-03-05 00:34:54 -05:00
isa Fix up some ISA related stuff. 2006-08-02 12:07:44 -04:00
linux Merge zizzer:/bk/multiarch 2006-03-09 15:56:42 -05:00
tru64 Get rid of obsolete header that had only one declaration of 2006-03-12 01:05:01 -05:00
aout_machdep.h Many files: 2005-06-05 05:16:00 -04:00
arguments.cc Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
arguments.hh Many files: 2005-06-05 05:16:00 -04:00
ecoff_machdep.h Many files: 2005-06-05 04:21:22 -04:00
ev5.cc Updates for registers and stuff. 2006-08-02 12:04:18 -04:00
ev5.hh Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. 2006-02-19 02:34:37 -05:00
faults.cc Move TLB faults into the normal fault classes. Now they are executed when the fault is invoked. 2006-04-22 18:09:08 -04:00
faults.hh Move TLB faults into the normal fault classes. Now they are executed when the fault is invoked. 2006-04-22 18:09:08 -04:00
isa_traits.hh Code update for CPU models. 2006-08-11 17:42:59 -04:00
osfpal.cc Many files: 2005-06-05 05:16:00 -04:00
osfpal.hh Many files: 2005-06-05 05:16:00 -04:00
process.cc Filled out the object file loader so it can load object files for several OSs and architectures. 2006-03-04 03:09:23 -05:00
process.hh Moved where some alpha specific source files were mentioned to be in the alpha specific Sconscript, and took advantage of the os specific directories for the process files. 2006-03-07 04:25:42 -05:00
SConscript no more common syscall emulation, now common for everyone 2006-03-09 15:42:09 -05:00
stacktrace.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
stacktrace.hh Made Addr a global type 2006-02-21 03:38:21 -05:00
system.cc Merge gblack@m5.eecs.umich.edu:/bk/multiarch 2006-03-04 22:32:13 -05:00
system.hh First cut at moving alpha specefic stuff out of /sim/system* into 2006-03-03 14:24:15 -05:00
tlb.cc Move TLB faults into the normal fault classes. Now they are executed when the fault is invoked. 2006-04-22 18:09:08 -04:00
tlb.hh Move TLB faults into the normal fault classes. Now they are executed when the fault is invoked. 2006-04-22 18:09:08 -04:00
vtophys.cc Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
vtophys.hh Made Addr a global type 2006-02-21 03:38:21 -05:00