Anthony Gutierrez 0b3897fc90 O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs ... This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation.		2012-08-15 10:38:08 -04:00
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prefetch	gem5: fix some iterator use and erase bugs	2012-05-10 18:04:27 -05:00
tags	Fix: Address a few benign memory leaks	2012-07-09 12:35:30 -04:00
base.cc	O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs	2012-08-15 10:38:08 -04:00
base.hh	Port: Move retry from port base class to Master/SlavePort	2012-07-09 12:35:31 -04:00
BaseCache.py	cache: Allow main memory to be at disjoint address ranges.	2012-03-09 09:59:25 -05:00
blk.cc	Fix #include lines for renamed cache files.	2008-02-10 14:45:25 -08:00
blk.hh	mem: fix cache stats to use request ids correctly	2012-02-12 16:07:39 -06:00
builder.cc	MEM: Introduce the master/slave port sub-classes in C++	2012-03-30 09:40:11 -04:00
cache.cc	remove the totally obsolete split cache	2008-10-23 16:11:28 -04:00
cache.hh	Port: Make getAddrRanges const	2012-07-09 12:35:34 -04:00
cache_impl.hh	cache: don't allow dirty data in the i-cache	2012-07-27 16:08:04 -04:00
mshr.cc	Fix: Address a few benign memory leaks	2012-07-09 12:35:30 -04:00
mshr.hh	Replace curTick global variable with accessor functions.	2011-01-07 21:50:29 -08:00
mshr_queue.cc	cache: coherence protocol enhancements & bug fixes	2010-09-09 14:40:18 -04:00
mshr_queue.hh	includes: sort all includes	2011-04-15 10:44:06 -07:00
SConscript	scons: rename TraceFlags to DebugFlags	2011-06-02 17:36:21 -07:00