70b35bab57
They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76 |
||
---|---|---|
.. | ||
alpha_access.h | ||
alpha_console.cc | ||
alpha_console.hh | ||
baddev.cc | ||
baddev.hh | ||
disk_image.cc | ||
disk_image.hh | ||
etherbus.cc | ||
etherbus.hh | ||
etherdump.cc | ||
etherdump.hh | ||
etherint.cc | ||
etherint.hh | ||
etherlink.cc | ||
etherlink.hh | ||
etherpkt.cc | ||
etherpkt.hh | ||
ethertap.cc | ||
ethertap.hh | ||
ide_atareg.h | ||
ide_ctrl.cc | ||
ide_ctrl.hh | ||
ide_disk.cc | ||
ide_disk.hh | ||
ide_wdcreg.h | ||
io_device.cc | ||
io_device.hh | ||
isa_fake.cc | ||
isa_fake.hh | ||
ns_gige.cc | ||
ns_gige.hh | ||
ns_gige_reg.h | ||
pciconfigall.cc | ||
pciconfigall.hh | ||
pcidev.cc | ||
pcidev.hh | ||
pcireg.h | ||
pitreg.h | ||
pktfifo.cc | ||
pktfifo.hh | ||
platform.cc | ||
platform.hh | ||
rtcreg.h | ||
simconsole.cc | ||
simconsole.hh | ||
simple_disk.cc | ||
simple_disk.hh | ||
sinic.cc | ||
sinic.hh | ||
sinicreg.hh | ||
tsunami.cc | ||
tsunami.hh | ||
tsunami_cchip.cc | ||
tsunami_cchip.hh | ||
tsunami_io.cc | ||
tsunami_io.hh | ||
tsunami_pchip.cc | ||
tsunami_pchip.hh | ||
tsunamireg.h | ||
uart.cc | ||
uart.hh | ||
uart8250.cc | ||
uart8250.hh |