358fdc2a40
This is to avoid condition code based dependences from effectively serializing instructions when the instruction doesn't actually use them.
193 lines
8.8 KiB
C++
193 lines
8.8 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'sh' : ('signed int', 16),
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'uh' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'ud' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64)
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}};
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let {{
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maybePCRead = '''
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((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
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xc->%(func)s(this, %(op_idx)s))
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'''
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maybeAlignedPCRead = '''
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((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
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xc->%(func)s(this, %(op_idx)s))
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'''
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maybePCWrite = '''
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((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
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xc->%(func)s(this, %(op_idx)s, %(final_val)s))
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'''
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maybeIWPCWrite = '''
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((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
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xc->%(func)s(this, %(op_idx)s, %(final_val)s))
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'''
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maybeAIWPCWrite = '''
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if (%(reg_idx)s == PCReg) {
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bool thumb = THUMB;
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if (thumb) {
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setNextPC(xc, %(final_val)s);
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} else {
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setIWNextPC(xc, %(final_val)s);
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}
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} else {
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xc->%(func)s(this, %(op_idx)s, %(final_val)s);
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}
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'''
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readNPC = 'xc->readNextPC() & ~PcModeMask'
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writeNPC = 'setNextPC(xc, %(final_val)s)'
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writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
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forceNPC = 'xc->setNextPC(%(final_val)s)'
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}};
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def operands {{
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#Abstracted integer reg operands
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'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
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'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
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'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
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'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
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'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
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'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
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'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
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'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
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'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
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'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
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'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
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maybePCRead, maybeIWPCWrite),
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'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
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maybePCRead, maybeAIWPCWrite),
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'SpMode': ('IntReg', 'uw',
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'intRegInMode((OperatingMode)regMode, INTREG_SP)',
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'IsInteger', 2),
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'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
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'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
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maybeAlignedPCRead, maybePCWrite),
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'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
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'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
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'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
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'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
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'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
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'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
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'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
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'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
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'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
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'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
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'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
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'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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#General Purpose Integer Reg Operands
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'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
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'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
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'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
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'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
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'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
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'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
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'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
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'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
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'OptCondCodes': ('IntReg', 'uw',
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'''(condCode == COND_AL || condCode == COND_UC) ?
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INTREG_ZERO : INTREG_CONDCODES''', None, 2),
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#Register fields for microops
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'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
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'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
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maybePCRead, maybeIWPCWrite),
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'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
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'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
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#General Purpose Floating Point Reg Operands
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'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
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'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
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'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
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#Memory Operand
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'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
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'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
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'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2),
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'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
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'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
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'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
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'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
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'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
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'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2),
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'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
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'PC': ('PC', 'ud', None, None, 2),
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'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
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readNPC, writeNPC),
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'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
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readNPC, forceNPC),
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'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
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readNPC, writeIWNPC),
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}};
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