Ali Saidi 4e8d2d1593 make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads ... src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly --HG-- extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42		2007-03-02 22:34:51 -05:00
..
cache	rename store conditional stuff as extra data so it can be used for conditional swaps as well	2007-02-12 13:06:30 -05:00
config	Backing in more changsets, getting closer to compile	2006-06-28 14:35:00 -04:00
bridge.cc	Update bus bridges now that snoop ranges are passed properly	2006-11-14 01:12:52 -05:00
bridge.hh	Use PacketPtr everywhere	2006-10-20 00:10:12 -07:00
bus.cc	More DPRINTF cleanup.	2007-02-06 23:53:48 -08:00
bus.hh	Minor DPRINTF fixes.	2007-02-06 21:53:05 -08:00
dram.cc	make our code a little more standards compliant	2007-01-26 18:48:51 -05:00
dram.hh	Use PacketPtr everywhere	2006-10-20 00:10:12 -07:00
mem_object.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
mem_object.hh	Fix up doxygen.	2006-08-14 19:25:07 -04:00
packet.cc	rename store conditional stuff as extra data so it can be used for conditional swaps as well	2007-02-12 13:06:30 -05:00
packet.hh	rename store conditional stuff as extra data so it can be used for conditional swaps as well	2007-02-12 13:06:30 -05:00
packet_access.hh	make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads	2007-03-02 22:34:51 -05:00
page_table.cc	initialize end, clean up loop	2006-10-19 23:35:59 -07:00
page_table.hh	add code to serialize se structures. Lisa is working on the python side of things and will test	2006-10-17 19:38:36 -04:00
physical.cc	some forgotten commits	2007-02-12 18:40:08 -05:00
physical.hh	rename store conditional stuff as extra data so it can be used for conditional swaps as well	2007-02-12 13:06:30 -05:00
port.cc	Make memory commands dense again to avoid cache stat table explosion.	2007-02-07 10:53:37 -08:00
port.hh	Make memory commands dense again to avoid cache stat table explosion.	2007-02-07 10:53:37 -08:00
port_impl.hh	Put the ProcessInfo and StackTrace objects into the ISA namespaces.	2006-11-08 00:52:04 -05:00
request.hh	rename store conditional stuff as extra data so it can be used for conditional swaps as well	2007-02-12 13:06:30 -05:00
tport.cc	Make memory commands dense again to avoid cache stat table explosion.	2007-02-07 10:53:37 -08:00
tport.hh	Merge ktlim@zizzer:/bk/newmem	2006-10-31 14:37:19 -05:00
translating_port.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
translating_port.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
vport.cc	implement vtophys and 32bit gdb support	2007-02-18 19:57:46 -05:00
vport.hh	implement vtophys and 32bit gdb support	2007-02-18 19:57:46 -05:00